A Math Question: Does IoT = SoC?

Few electronics-related topics have been more widely discussed in the past year or so than the prospects for the so-called Internet of Things (IoT), sometimes called the Internet of Everything (IoE). Hardware and software vendors have been falling all over themselves trying to ride the presumed IoT juggernaut. EDA has not been immune. In its roundup of attendee feedback from this year’s Design Automation Conference (DAC), the DeepChip site quoted a user saying, “The ubiquity of IoT. After 6 hours into DAC, I was ready to slap the next vendor who used that buzzword.”

The trumpeting of IoT was even greater at ARM TechCon, not surprising because of its focus on embedded systems. Here at Breker, we’ve used the term sparingly because it’s not really clear exactly what the IoT will become. Certainly there will be many more nodes of all sorts connected to the Internet in coming years, but there are numerous open questions. Our main interest is whether the IoT will result in an explosion of new SoC designs, and hence a broader market for our verification solutions. This blog post doesn’t provide a firm answer since none is possible yet, but it’s a topic worth addressing.

First, it’s important to note that the IoT term implies the connection of many traditionally “dumb” devices. The number of smart phones, tablets, and computing devices in general continues to grow, and virtually all of these are on the Internet. It’s the connection of much simpler devices–thermostats, appliances, lights, cameras, motion sensors, biometric monitors, RFID tags, etc.–that potentially changes the scope of the Internet as we know it today. The number of connected nodes could rise to thousands of times what we have now.

There are many questions about how all this will come together. There is a dearth of standards for intercommunication of devices and, on the flip side, for device security. Some of the scenarios being painted in the popular press, such as someone hacking your refrigerator and ruining all your food, are entertaining yet plausible. Theft of personal data, including biometrics, is equally plausible but far more likely. These topics are beyond the scope of this post; we would like to hone in on the question of how the interconnected devices will be built.

It seems likely that the chips underlying most IoT nodes will contain at least one processor and therefore quality as SoCs. Dealing with complex protocols and security methods requires computing power. Further, having a good chunk of a chip’s functionality in software allows for upgrades to fix bugs or adapt to changes in protocol or security standards. As we pointed out in a recent Chip Design magazine article, many IoT nodes will be located in hard-to-reach places. If something goes wrong during a software update over the network, the end user will have little recourse.

This argues for a very well verified SoC, so that software updates will not be needed to fix bugs. Most hardware updates will be virtually impossible, so the chip itself must be extremely robust. These requirements can be satisfied only with more thorough verification, and we believe that our products can and will play a key role. We can verify at every stage of SoC development, including fabricated silicon in the lab. Even if the SoC is an FPGA rather than a custom chip, verification is no less essential since reprogramming a device in the field to fix a bug is unrealistic.

Perhaps the most interesting question is whether the IoT market will require many unique chips, each of which must be verified and built, or will be satisfied by a few standard parts. This question came up two months ago at the Silicon Valley IP Users Conference, and the TSMC representative responded that we are in a period of SoC customization. IoT nodes will be very cost-sensitive, so designers will not want to pay extra for a generic chip with irrelevant content. This scenario is also good news for Breker, since the more SoCs designed the more need for leading-edge verification tools.

Finally, if we accept the TSMC prediction, IoT suppliers are going to be pumping out lots of similar chips, each tuned for its end application but containing many common building blocks. As we noted in a recent SemiconductorEngineering article, one of the weaknesses of traditional verification methodologies is limited reuse from block to chip level. The graph-based scenario models that we use to generate test cases can be easily composed at higher levels of hierarchy, enabling effective verification reuse from block to cluster to subsystem to full SoC.

Perhaps the IoT is over-hyped. A recent commentary in The Economist argued that security concerns and other issues will limit the massive growth predicted. But as long as more nodes are added to the Internet and more SoC devices are designed, the need for verification and the opportunity for innovative solutions will continue to grow. That will be good news for us and we will continue to evolve our product line as needed for our IoT customers. If you have thoughts on this market and the current level of buzz around it, please submit a comment.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: ARM TechCon, Breker, dac, EDA, functional verification, graph, IoE, IoT, reuse, scenario model, SoC verification

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