Some Thoughts on SIPs, VIPs, and SMIPs

In my recent report from the Silicon Valley IP Users Conference, I passed on the prediction that the compound annual growth rate (CAGR) of semiconductor (SIP) is expected to be 12% for the next five years. Clearly there is a growing need for portions of huge SoCs to be pre-designed, pre-verified, and delivered as reusable SIP. This is a trend that started about 20 years ago with the earliest SIP vendors selling libraries and cores for standardized functions along with verification IP (VIP) to support their use.

The IP (SIP and VIP) industry has evolved a lot since then. The most obvious change is that it has been largely consumed by the major EDA companies. Synopsys and Cadence, in particular, have made many acquisitions in this space over the past few years. Some of the price tags have been quite impressive:  US$380M  for Tensilica, US$315M for Virage, and about the same price for Denali. In this post, I’d like to share some thoughts on the evolution of the IP business.

Let me admit my deep personal interest in this topic. I’ve been in the EDA industry for 15 years, but took a half-step there in 1995 when I moved from being manager of a chip design team at AMD to VP of Engineering at a pioneering semiconductor IP (SIP) startup called Virtual Chips. We developed and sold synthesizable cores for PCI, USB, IEEE 1394, and other standard interface protocols. These cores were designed for reuse, including a number of features and options for different target applications.

In addition to providing the RTL for the SIP, we offered limited verification IP (VIP) components for the user to check that the cores worked “out of the box” and to assist them in verifying the chips containing the cores. The VIP was not really designed for engineers who wanted to create their own interface designs, since we would much rather sell them the core as well. It was an exciting time in an emerging business. Virtual Chips was acquired by Phoenix Technologies, spun out as inSilicon, and eventually acquired by Synopsys.

I had lunch yesterday with an old Phoenix friend who is still happily employed at Synopsys, and that’s partly what promoted the idea for this post. We talked about how the IP business has proven crucial as a growth area for EDA, and also the pluses and minuses of trying to run an IP business within the rather different business model of EDA software. Of course there is leverage from a large company, but the tight focus of a dedicated company is surely one reason why ARM, CEVA, Imagination Technologies, and others continue as stand-alone SIP and/or VIP providers.

I fully expect both EDA and standalone IP companies to continue to grow and thrive by satisfying the need for SIP content in SoC designs. While Cadence and Synopsys have both been very successful in this space, I do see some clear advantages to independence. This topic arose via an interesting comment that was posted to my conference report, asking whether most SIP usage was truly as drop-in as the vendors like to promote or whether there is customization required.

My response was that smaller IP providers are more likely to customize SIP and offer consulting services, whereas the EDA companies and larger IP providers have a clear focus on automating their products to support a wide range of options and eliminate the need for most customization. We started down that path years ago at Virtual Chips and it’s fascinating to see how much technology has been developed. We tried to avoid customization since it was hard to keep multiple versions of a core synchronized as bugs were found or the standards were updated.

I have been fortunate to be involved in the VIP products of all the EDA companies where I’ve worked, and thus able to nurture my passion for IP-related topics. Most of you are probably wondering what this means at Breker, since we do not generally advertise ourselves as being in the IP business.  This is changing, as we hinted when introducing our Coherency TrekApp and the scenario model IP (SMIP) that underlines it. In the next blog post, I’ll fill in more details on how we work with SIPs, VIPs, and SMIPs.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Breker, cache coherency, Cadence, EDA, functional verification, IP, reuse, scenario model, semiconductor IP, SIP, SMIP, SoC verification, Synopsys, TrekApp, verification IP, VIP

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