If Your SoC Is Not Cache Coherent, It Soon Will Be

In last week’s post, we discussed in detail how Breker’s TrekSoC and TrekSoC-Si products can verify the performance of your SoC by stressing every aspect of its functionality. Shortly before that, we announced a partnership with Carbon Design Systems to complement their fast, accurate processor models with TrekSoC. About two months ago, we introduced the new Coherency TrekApp and described how it can verify multi-processor cache coherency with minimal effort.

You can see a strong theme here: multi-processor SoC designs, fast simulation models, automatic generation of multi-threaded, multi-processor test cases, and test cases powerful enough to gather realistic performance metrics from pre-silicon simulation. But what if you don’t have multiple processors or caches in your SoC design? There’s a clear sense emerging in the industry that more and more chips are becoming multi-processor SoCs, and most of these will require cache coherency for the CPU clusters and beyond. Let’s explore this topic more in this post.

Over the last few years, many SoCs have evolved to add multiple processors. As more processors share common memory, it is natural for caches to be added both to reduce memory latency and to minimize conflict when multiple processors try to access the same memory. Any multi-processor cache structure requires coherency. For example, if CPU A updates a memory address that’s in the cache of CPU B, then the cache line containing that address must be updated or invalidated. Otherwise CPU B will get the wrong value if it reads from that same address.

Many smart phones and other consumer devices already contain multiple embedded processors, and it’s just a matter of time before they contain multi-level, coherent caches. The interconnect fabric IP providers are moving toward coherent architectures, or will need to do so soon in order to remain competitive. It seems clear that if you are developing almost any sort of SoC you will soon be designing and verifying a chip with multiple processors and multi-level caches.  It’s just a matter of time, and probably months rather than years.

Some of you are asking why you need to worry about coherency if you license your multi-core processor clusters from an IP vendor or your silicon provider. Surely you can trust ARM or Imagination (MIPS) or Intel to get their clusters correct, including cache coherency? Maybe so, but we are also seeing that many SoC designs are requiring coherency beyond pre-packaged CPU clusters. For a start, we see some companies hooking up multiple clusters and having to provide their own coherent link and possibly an additional higher-level cache.

Further, other agents that access memory are becoming at least partially coherent. If a DMA controller writes data to a memory address that’s in the cache of a CPU, then we’re back in the same coherency scenario we discussed earlier. The controller may have its own cache, but even if it doesn’t it must take into account the caches for other agents accessing shared memory. Cache coherency used to be a worry only for CPU designers. Increasingly, it’s part of every SoC team’s verification challenge. If it’s not an issue for you yet, it will be. So let’s conclude by reviewing what Breker can do to help.

TrekSoC and our Coherency TrekApp are out-of-the-box solutions for verifying multi-processor cache coherency. The app includes a scenario model pre-populated with almost everything needed. You simply specify the configuration of your processors, caches, and memories. It is easy to extend the model to include DMA engines and other agents that also access memory and also require some level of coherency. TrekSoC automatically generates a set of complex test cases that will stress-test your coherent subsystem in simulation.

The CPAK processor models from Carbon provide an excellent platform on which to run these test cases. In the process, you’re stressing your design very well. As Carbon phrases it, “Users can optimize the system using multiple benchmarks for performance exploration, combining realistic system traffic to understand cache statistics, memory throughput and latency, and validate assumptions made during the design process under various workloads.” So, you can measure the performance of your SoC at the same time you’re verifying its functionality.

Of course, you can build on the scenario models used for cache coherency verification to model your complete SoC and its verification plan. So performance metrics can extend from CPU clusters to subsystems to full chip. You can also use TrekSoC-Si to generate test cases tuned for hardware platforms (emulators, FPGA prototypes, and silicon in the lab) to extend the verification and performance benefits beyond simulation.  If you’re in the cache-coherent world today, or about to move there on your next project, please contact us to learn more.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Breker, cache, Carbon, coherency, CPAK, DV, functional verification, IoT, IP, portable stimulus, SoC, SoC verification, TrekApp, TrekSoC, TrekSoC-Si, uvm, VIP

This entry was posted on Thursday, October 30th, 2014 at 3:52 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.