A Fond Farewell to DAC 51 in San Francisco

The 51st Design Automation Conference (DAC) has passed into the history books with three days of exhibits and a wide range of enveloping technical sessions and tutorials. After returning home, I’m thinking back over the week fondly as I nurse feet that ache more than I thought possible. Before I get back into the usual work routine, I want to capture some of the impressions and thoughts running through my head.

There is no doubt that  big forces in the industry are aligning toward our view of SoC verification with graph-based scenario models. Many of the people who stopped by our “USS Ice Breker” booth completely understood that they risked hitting an iceberg with their minimal full-chip verification efforts. Some had heard about Breker from colleagues or had seen us listed in Gary Smith’s and John Cooley’s DAC “must see” lists. Others knew little about us but were attracted by our claim as “The SoC Verification Company.” All wanted to know how we can help them.

As I discussed a couple of weeks ago, Accellera has formed the Portable Stimulus Specification Proposed Working Group (PWG) to consider standardization of graph-based verification and similar approaches that complement and supplement its UVM testbench standard. Several visitors to the booth asked about this effort and commented that it was a sign that our ideas on SoC Verification are becoming more mainstream.

If further proof is needed, our long-time customer IBM participated on the show floor in a Pavilion Panel called “The Asymptote of Verification.” I thought that Wolfgang Roesner  did an excellent job talking about the unique attributes of graph-based scenario models, including starting from the intended goal and being able to deterministically generate a test case to get there. He also made the important point that graphs are an effective way to communicate design intent between designers and verification engineers.

If there was a new theme for us at DAC this year, it was the importance of an ecosystem for any emerging technology or methodology. Prior to the show, we announced two consulting partnerships, a VIP partnership, and an expansion of our relationship with Synopsys to include the Verdi Interoperable Apps (VIA) Access Program. We had several promising meetings in our suite with other potential partners as well. I see the increased interest in working with Breker as another sign of the world moving in our direction.

All three of the demonstrations in our booth proved quite popular. As I previewed last week, we showed TrekSoC-Si running our multi-threaded test cases within a multi-processor TI OMAP family SoC on a production board and we highlighted our new integration with Verdi’s advanced debug features. We added a third demo as well, showing how our graph-based scenario models are reusable from IP blocks through subsystems to complete SoCs.

Although floor traffic seemed light for DAC in San Francisco, I was pleased with both the quantity and quality of the leads we gathered. I apologize if this post seems a bit too self-congratulatory but, honestly, all of us at Breker came away feeling energized from an excellent show. I think that we are moving from being pioneers with arrows in our back to knights leading the charge for better SoC verification supported by the massed forces of competitors, partners, and Accellera. With that grandiose mixed metaphor, I’ll close by thanking everyone who stopped by to visit us. See you next year back in Moscone Center!

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: austin, Breker, dac, dvcon, EDA, formal analysis, functional verification, graph, IBM, partnerships, portable stimulus, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si, Verdi

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