Archive for May, 2014
Wednesday, May 28th, 2014
DAC is back, Jack! The big show returns to San Francisco for two years before heading back to Austin. Last year was a special one for Breker, with our 10th anniversary as a company, the 50th year of DAC, and the first time for the show in Austin, our birthplace. But no location draws more visitors and more buzz than San Francisco. It’s a short train ride from traditional Silicon Valley and arguably part of an extended definition of Silicon Valley that includes a fair chunk of the Bay Area.
This year’s show promises plenty of excitement, and we’d like to fill you in. Of course, we will be there as part of the always lively exhibit floor. Those of you who attended DAC in Austin will surely remember our naval-themed “USS Ice Breker” booth, which we loved so much we’re shipping it to San Francisco. No visit to the DAC exhibits would be complete without stopping by to see Breker in booth 2602 and taking a “cruise” with us. You can request a meeting at a specific time by visiting our DAC signup page.
(more…)
Tags: austin, Breker, dac, dvcon, EDA, formal analysis, functional verification, graph, IBM, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si, Verdi
No Comments »
Tuesday, May 20th, 2014
Many newcomers to Breker’s Web site comment that they are impressed by the quantity and quality of the material located or linked there. For a small company, Breker does publish a lot. Our site links to nearly 250 items from the last two-and-a-half years: conference papers, technical articles, blog posts, press releases, interviews, press coverage, and more. On average, something by or about Breker appears online twice a week, not counting social media alerts or the content hosted on our own site.
Of course this takes a lot of effort by Breker employees, but this level of production would not be possible without the expertise of Nanette Collins, whose marketing and public relations agency has been instrumental in the success of many EDA companies. We thank her for her efforts and welcome her as a guest blogger today. Nanette shares her thoughts on the upcoming (June 2-4) Design Automation Conference (DAC) in San Francisco:
(more…)
Tags: Boston Marathon, Breker, dac, EDA, functional verification, marathon, race, SoC verification
No Comments »
Tuesday, May 13th, 2014
As regular readers know, Breker’s claim to fame is the automatic generation of multi-threaded, self-verifying test cases that run on multiple heterogeneous processors within an SoC. The source for the generation process is a graph-based scenario model that captures the design intent and verification space. We chose graphs as an enabling technology more than ten years ago for a number of reasons, some of which we’ll discuss in this post.
The catalyst for this discussion is a new effort within the Accellera standards body to form the Portable Stimulus Specification Proposed Working Group (PWG). Basically, Accellera has formed a proposed working group to determine whether a technical working group should be established to start developing a specification for a standard. What does this have to do with graphs, and Breker? We’ll do our best to explain the history and current status.
(more…)
Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, mentor, portable stimulus, pwg, reuse, scenario model, SoC verification, standards, test generation, working group
No Comments »
Tuesday, May 6th, 2014
Last week I used a talk by Vigyan Singhal, CEO of formal consulting experts Oski Technology, as the springboard for a blog post on how to extend verification planning for formal analysis and graph-based SoC verification. This week, I’m using a panel held at that same “Decoding Formal Club” meeting as the starting point for my thoughts on how to establish an effective team to use relatively new verification technologies such as formal and graphs.
The second half of the meeting was a panel on “How to Build a Productive Formal Team” moderated by Harry Foster from Mentor. The participants included a nice mix of users, while Vigyan rounded out the panel with his unique blend of formal tool development and hands-on usage with many customers. Although there wasn’t much controversy per se, it was clear that everyone had different experiences leading to different opinions on how to build a strong formal team.
(more…)
Tags: Breker, constraints, decoding formal, formal analysis, functional verification, graph, jasper, oski, scenario model, simulation, SoC verification
No Comments »
|
