The Dawn of the Embedded Verification Engineer

Some readers may recall that I was on the panel “Is Software the Missing Piece In Verification?” at this year’s DVCon. I mentioned a bit about it in my summary of that show, and moderator Ed Sperling has done an outstanding job of transcribing the panel discussion and transforming it into one of his signature “Experts at the Table” three part series on SemiconductorEngineering. I encourage you to read all three parts since a bunch of interesting topics came up.

Cadence recently published an odd blog post that appeared to be based on the panel: it showed a photo of the panelists and included quotes from several of them, although it mentioned neither DVCon nor the panel. Perhaps they were trying to make it sound as if they held a separate event. They quoted their own representative, the panelist from Vayavya, and the panelist from Intel (although they didn’t list his affiliation). But they did hit on one of the more lively topics of the panel: the changing role of the verification engineer.

I’ve extracted a few comments from Ed’s complete articles to show the line of discussion:

• Ken Knowlson of Intel talked about the “tension between the validation software folks and the production software folks” on SoC projects
• Cadence’s Frank Schirrmeister agreed and said “no one person exists who understands all of the details on the software side and the hardware side”
• Steve Chappell from Synopsys talked about the need for a “common language between the hardware guys and the software guys”
• Frank asked “do we need a new species of designer?” and Ken introduced the notion of the “glue engineers” who know both firmware and design
• I responded that “there is a hybrid skill set occurring as a result of this cooperation” between embedded programmers and verification engineers

I’m not sure that I have a great name for this emerging role, but let’s say “embedded verification engineer” for the purposes of this post. This matches what I see happening in the industry. As soon as SoC teams try to verify full chips in simulation, they realize that they need to run test software on the embedded processors. Verification engineers generally know C/C++ in addition to SystemVerilog, buy they don’t necessarily know all the tricks for writing efficient embedded code.

Frequently some embedded programmers are loaned to the verification effort. They pick up knowledge about RTL, Universal Verification Methodology (UVM) testbenches, and simulation. In turn, the verification team learns something about embedded programming. There is a hybrid engineer emerging from this process. When customers adopt TrekSoC to automatically generate C tests cases rather than hand-write tests, some of the users are verification engineers and some are embedded programmers, so the embedded verification engineer is the perfect fit.

In general, I see the lines blurring between the embedded domain and traditional EDA. I included the acceleration of this merger as one of my industry predictions for this year. The rise of the embedded verification engineer is just one example of this trend, albeit an example very important for Breker. Another of my predictions is that EDA vendors are more likely to acquire embedded vendors than vice-versa since EDA already spans the complete hardware and software SoC development process.

Do you agree? Do you see a blending and merging of skill sets on your current SoC projects? If not, could you imagine it happening soon? Do you have a better name for this new engineer with hybrid skills? Please feel free to comment so that we can get a dialogue going.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Breker, Cadence, dvcon, embedded programming, functional verification, hybrid, Intel, SoC verification, software-driven verification, Synopsys

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