Archive for April, 2014
Tuesday, April 29th, 2014
Last week I mentioned that I attended the third “Decoding Formal Club” meeting sponsored by formal consulting experts Oski Technology. I started out to write about this event but was distracted by the big news that Cadence had acquired formal leader Jasper Design Automation for $170M. As the meeting was winding up, a friend from Mentor picked up the news alert and showed it to me. I pulled up the news on my own smartphone and showed it to Vigyan Singhal, CEO of Oski and also the original founder of Jasper.
So I had the pleasure of informing Jasper’s founder that his old company had been acquired. But I don’t want to let that bit of fun or the Jasper news in general to lead us to forget about the Decoding Formal meeting. There were two primary segments: a presentation from Vigyan on verification planning and a panel of expert users on building a formal team. I’ll talk about the presentation today and cover the panel in a future post.
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Tags: Breker, Cadence, constrained-random, constraints, decoding formal, formal analysis, functional verification, graph, jasper, oski, scenario model, SoC verification, UCIS
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Tuesday, April 22nd, 2014
Yesterday may well go down in EDA history as one of the most important days in the evolution of the market for formal analysis. If you had asked me why yesterday morning, I would have said it was because I was attending the third “Decoding Formal Club” meeting sponsored by formal consulting experts Oski Technology. The range of companies represented there, and the enthusiasm for the topic, was a clear indication that formal has become an A-list technology for many verification teams.
So I planned to write today’s post about this meeting. But then, just as it was ending and Oski was thanking all the participants, news broke that Cadence had acquired formal leader Jasper Design Automation for $170M. Of course, this news was of intense interest to the attendees. It made yesterday “Acquisition Day” for formal analysis, so I’ll dub it “A-Day” and provide some thoughts in this post. I will talk a bit about the meeting as well, but will go into more details about the material presented in a future post.
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Tags: 0-In Design Automation, Breker, Cadence, EDA, equivalence checking, formal analysis, functional verification, jasper, mentor, simulation, SoC verification, Synopsys, Verplex
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Tuesday, April 15th, 2014
Last week I published a commentary on the Electronic Engineering Times site about the recent growth in the hardware emulation market. I noted that hardware-based platforms have become almost as big a market as software simulation and that some industry projections see them becoming dominant over the next few years. Of course, our friends at Jasper are predicting that formal will become the dominant verification technology, so it will be fun watching a three-way race.
For this post, I want to dig a bit deeper on hardware platforms in general. Historically, such platforms have been divided into three categories: simulation acceleration, in-circuit emulation (ICE), and FPGA prototyping. The reality is that these are no longer clearly distinct categories; there is a lot of fuzziness and even some overlap. While the market for all three types of hardware platforms is growing, I find that my observations and opinions vary depending upon which specific solution I’m considering.
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Tags: Breker, EDA, emulation, formal analysis, FPGA prototyping, functional verification, jasper, simulation, SoC verification, TrekSoC-Si
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Tuesday, April 8th, 2014
Some readers may recall that I was on the panel “Is Software the Missing Piece In Verification?” at this year’s DVCon. I mentioned a bit about it in my summary of that show, and moderator Ed Sperling has done an outstanding job of transcribing the panel discussion and transforming it into one of his signature “Experts at the Table” three part series on SemiconductorEngineering. I encourage you to read all three parts since a bunch of interesting topics came up.
Cadence recently published an odd blog post that appeared to be based on the panel: it showed a photo of the panelists and included quotes from several of them, although it mentioned neither DVCon nor the panel. Perhaps they were trying to make it sound as if they held a separate event. They quoted their own representative, the panelist from Vayavya, and the panelist from Intel (although they didn’t list his affiliation). But they did hit on one of the more lively topics of the panel: the changing role of the verification engineer.
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Tags: Breker, Cadence, dvcon, embedded programming, functional verification, hybrid, Intel, SoC verification, software-driven verification, Synopsys
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Tuesday, April 1st, 2014
In our last post, we discussed some details of the demo that we showed at the DVCon and SNUG Silicon Valley events, in which TrekSoC-Si generated a test case, downloaded it into a commercial SoC (a TI OMAP4430 with dual ARM cores), and ran it in the actual chip. Our focus last time was on Breker’s unique visualization for the multi-threaded, multi-processor test cases that we generate. Specifically, we provide the same display for a test case running in silicon as we do for one running in simulation or simulation acceleration.
Even more interesting is our ability to display coverage information for test cases running in silicon. You might think that this is impossible unless we’re building coverage structures into the SoC that you fabricate. Customers have been known to build specific types of coverage metrics into their hardware, for example real-time monitoring of bus bandwidth and SoC performance. But that’s not what we’re doing; we can gather highly accurate system-level overage without changing the design a bit.
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Tags: Breker, dvcon, EDA, emulation, functional verification, goals, graph, paths, reuse, scenario model, silicon, simulation, SNUG, SoC verification, system coverage, TrekSoC, use cases
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