Final Report on the Big DVCon 2014 Show

In our last two posts, we talked about the 2014 edition of the Design & Verification Conference & Exhibition, DVCon, in San Jose. Now that the show is history, lots of bloggers are summarizing their experience. Since I thought that this was an excellent event all around, allow me to join the chorus of voices praising DVCon 2014.

Here at Breker, our biggest effort goes toward the exhibition. Although it’s a relatively small booth and exhibit floor, we do want to put our best foot forward. So we had all-new signage this year updating attendees on our products and their capabilities. We also showed a very different demo from last year, with our TrekSoC-Si product generating a test case, downloading it into a commercial SoC (a TI OMAP4430), and running in the actual chip. We chose to repeat our very popular giveaway from DAC: a combined flashlight and distress whistle that will come in handy if you perform inadequate SoC verification and hit an iceberg.

I don’t mean to suggest that a conference exhibit means work only for us Marketing types. Anyone in EDA can tell you that the applications engineers burn some midnight oil refining the demos, and it’s not unusual for R&D to be scrambling to fit in a few final features that will give the demos more impact. Everything came together nicely and we had a very good turnout at the booth. More people stopped by this year than last, but more importantly I felt that a high percentage “got” what we do and are now facing, or will face soon, a whole new level of verification challenge. We know that we can help these engineers succeed.

The second major aspect of the show for Breker was my participation on the panel “Is Software the Missing Piece In Verification?” on Wednesday. The panelists strongly agreed on one point: SoC verification can’t be performed effectively without software. The “verification from the inside out” approach that we’ve been championing for several years is truly a mainstream concept now. Moderator Ed Sperling is transcribing the entire panel as one of his “experts at the table” series and you can now read the first part.

Much of the discussion focused on two kinds of software. The first is the production software that ships with the SoC; Cadence amusingly referred to this as the “Elvis software” because it leaves the building. Of course the production hardware and software must be co-verified before the SoC product is complete. The huge increase in sales of simulation accelerators, in-circuit emulators, and FPGA-based prototyping systems is due almost entirely to the desire to run operating systems and applications on a highly accurate model of the chip before it is fabricated.

But production code is not ready early in a project, runs too slowly in software simulation, provides few debugging features, and is not very effective at finding any lurking SoC hardware bugs. So verification teams spend a lot of time on “non-Elvis software” including tests hand-written or auto-generated for pre-silicon verification or post-silicon diagnostics. Of course, we advocate the use of graph-based scenario models to generate test cases that are efficient enough to run in simulation, easy to debug, and portable both vertically and horizontally over the course of the SoC project.

I pointed out that several of the vendors represented used graphs as a key verification technology and asked whether their were other similar technologies that we should consider on the panel. No one responded with anything specific, although the phrase “graphs and more” was bandied about. I’ll certainly be curious to see what “and more” turns out to be as additional products geared toward software-driven verification are announced.

Beyond the exhibits and the panel, there was a lot of other activity. I attended a few of the technical sessions and they were generally quite good. As Peggy Acinena reports in her DVCon blog post, a nice selection of posters drew good crowds and lively discussions. I was able to attend only one of the vendor-sponsored lunches (Mentor’s) but I heard that the others were also interesting with good food. Last but not least, the sponsored exhibit receptions offered more free food and various libations.

My final thought is a question: has DVCon finally outgrown the venerable DoubleTree hotel? The exhibits overflowed the ballroom into the lobby, but this didn’t seem to cause any problems. Some of the sessions were overcrowded although most were not. The biggest issue for me is a familiar one year after year: the long wait to pay for parking and the even longer wait to exit. If the DoubleTree can figure out how to improve this, I’ll be glad to attend shows there for a long time to come. See you there next year!

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, reuse, scenario model, simulation, SoC verification, test generation, TrekSoC-Si

This entry was posted on Monday, March 10th, 2014 at 6:52 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.