In a video interview at Silvaco’s Users Group event SURGE 2019 in Santa Clara, Stephen Fairbanks, Certus Semi CTO, talks about what is changing I/Os and ESD protection in nanometer SoCs.
Silvaco Nanometer Newsbyte 
Graham Bell
Graham is Sr. Director of Marketing at Silvaco Inc. An experienced semiconductor-design marketing strategist and avid blogger before joining Silvaco, Graham previously was VP of marketing at Uniquify, a fabless SoC product and IP company, and at Real Intent, a verification software company. In his … More » Video Interview: What’s Changing for I/Os and ESD Protection in Nanometer SoCsDecember 10th, 2019 by Graham Bell
Customer Case Study: Using SmartSpice to Deliver Next-Generation, Low Power Memory SystemsDecember 3rd, 2019 by Graham Bell
 At our SURGE Santa Clara users group event in October, Cameron Fisher, CEO of Mobile Semiconductor described their experience in adopting SmartSpice as their characterization engine for creating the database for their Trailblaze™ memory compiler software. Below is a summary of his talk. Free 350 pg. Book on SoC Designand Secure Autonomous Driving WebinarNovember 26th, 2019 by Graham Bell
Secure Autonomous Driving WebinarSilvaco has an upcoming webinar IP Solutions for Secure Autonomous Driving on Dec. 3, 10am – 11am (PST) . The webinar will present the risks and necessary countermeasures for securing cyber-physical vehicle systems. Manufacturers are pressured by customer demands and market competition to rapidly integrate the latest features into their vehicles, including Infotainment, 5G network connectivity, advanced driver assistance systems (ADAS), and autonomous driving. Increased vehicle-to-everything (V2X) connectivity exposes access to critical vehicle networks. ADAS and autonomous driving features yield physical control of a vehicle to software subsystems. These enhanced vehicles demand security hardening to guarantee the safety of pedestrians and motorists. How TCAD Can Optimize Power ElectronicsNovember 21st, 2019 by Graham Bell
The power electronics (PE) market is growing rapidly, driven by the accelerating demand of EV and HEV vehicles. Power devices lend themselves to design and manufacturing innovations at the transistor-level to improve device performance and reduce development and production costs. Silicon-carbide (SiC), gallium-nitride (GaN), and other wide bandgap materials have started to replace silicon in high-voltage power devices. Anyone designing and/or manufacturing silicon, SiC, or GaN technologies for the power device market, should use TCAD simulations as part of their R&D efforts, to understand their devices in greater detail and improve their key Figures of Merit. Silvaco TCAD is a market leader in simulation for power devices and its products have been used by foundries and fabless semiconductor companies, worldwide, for over 25 years. SmartSpice Does It SmartNovember 14th, 2019 by Graham Bell
According to the Merriam-Webster dictionary, two of the definitions for ‘smart’ are
By this definition, any SPICE simulator qualifies as a smart design tool, but what about versatility? SmartSpice has had over 30 years of product development and is the Swiss Army knife of circuit simulators, with wide applicability to different CAD design flows.  SMART Design at SEMICON Europa Tackles Atoms to Systems in Next-Generation SoCsNovember 11th, 2019 by Graham Bell
Silvaco’s CEO Babak Taheri enjoys telling the chip design community to think in terms of atoms for their next design project. In fact, he is urging the entire semiconductor ecosystem to consider the atomic level when designing next-generation SoC devices. In his view, these SoCs are driving the need for new memory architectures and photonic interfaces. He uses new, specialized IP as another example because IP requires analysis down to the nanometer and atomic levels on account of single nanometer process nodes. Babak takes his talk, “Next Generation SoC Design: From Atoms to Systems,” next week to SMART Design, the first system-centric series showcasing advances in electronic system design to be held at SEMICON Europa. SEMICON Europa will begin Tuesday, November 12, through Friday, November 15, at Messe München in Munich, Germany. SMART Design is scheduled for Thursday, November 14, from 14:30 until 17:30 in TechARENA 1, Hall B1. According to Babak, common wisdom dictates that each new chip design is more complex than the last and none is more complex than those currently under development. These new SoC devices for mobile phones, automobiles, intelligent edge nodes, big-data compute and storage are using AI and ML technologies that drive new bandwidth limited compute, data flow, and memory architectures. Some require photonic interfaces. One common denominator is the number of IP blocks. On the average, more than 85% of them are reused because it’s costly to make these chips again and again with new IP. Some estimates predict only 10% of IP used in an SoC design by 2025 will be new. Technologies that use and reuse design IP at the architectural level –– up to 90% –– include Flash memory, other advanced non-volatile memory technologies such as MRAM, RRAM and SoCs as well as NVIDIA’s Xavier and Apple’s A13. Read the rest of SMART Design at SEMICON Europa Tackles Atoms to Systems in Next-Generation SoCs AI and Machine Learning SoCs – Memory and Interconnect IP PerspectivesNovember 7th, 2019 by Graham Bell
The same day we hosted the Silvaco Users Group event (SURGE) in Silicon Valley on October 24, we also had an online webinar on artificial intelligence (AI) and machine learning (ML) SoCs from a memory and interconnect IP perspective. This webinar discussed the challenges of developing AI-based and ML-based SoCs and the novel architectures needed for AI and ML applications to meet efficiency requirements. These include specialized processing, high bandwidth and low-energy memory throughput, and reliable high-performance connectivity. The webinar also discussed the efficient customization of memory and interconnect IPs for successful development of AI and ML SoCs. To register and view this pre-recorded event, go to the AI and Machine Learning SoCs – Memory and Interconnect IP Perspectives page. PresenterAhmad S. Mazumder is the presenter for the webinar. He is a principal field application engineer in IP Engineering division of Silvaco. He is responsible for development and customer support in all analog and interface IPs. He is an industry veteran on the development of high-speed memory, interface IPs, and many types of analog IPs. He worked on cutting edge DDR, extreme high-speed SerDes, interfaces, ESD, and QoR for 24 years at various SoC companies (Intel, Broadcom, C-Cube Microsystems, etc). He recently joined Silvaco’s IP Engineering division. Ahmad S. Mazumder holds a MS in VLSI Semiconductor Design from the City University of New York and BS in Electrical and Electronics Engineering from Bangladesh University of Engineering and Technology. You Can Still Register for Silvaco SURGE Users’ Event in SV, Oct 24October 16th, 2019 by Graham Bell
SURGE Silicon ValleySilvaco continues on the great success of Silvaco Users Seminar at various Silvaco sites in 2019. SURGE brings the TCAD, EDA, and IP communities together to discuss new technologies, explore smart application integration, and discover innovative techniques for advanced semiconductor design. The event includes eight demo stations, a catered lunch, and cool prizes and giveaways for attendees.
Be sure to stay for a chance to win some great prizes!
AgendaRead the rest of You Can Still Register for Silvaco SURGE Users’ Event in SV, Oct 24 Webinar Preview: Fast Capacitance Extraction Within the Expert Layout EditorOctober 8th, 2019 by Graham Bell
Sungwon Kong, senior application engineer, sits down with Graham Bell to talk about his recent webinar Fast Capacitance Extraction Within the Expert Layout Editor Using Hipex and the Stellar Solver for a Touch Panel Application. To access the webinar click here. Click to watch the preview.
Everything You Want to Know about Silvaco Foundation IPSeptember 6th, 2019 by Graham Bell
In the creation of an ASIC or SoC a wide variety of digital components are needed. Standard logic cells are used to implement the high-level description of the chip which is typically written in RTL. A synthesis tool such as Design Compiler or RTL Compiler is used to generate a gate-level netlist built out of the standard logic cells from a cell library. Communication on and off of the chip, requires unique input/output cells or I/Os that can drive off-chip wiring and withstand electrostatic discharges in the range of thousands of volts. The other main category is digital memories typically SRAMS that can take up a significant amount of area on the die for a chip. These 3 categories of digital design IP are called Foundation IP. Silvaco offers a complete portfolio of SIPware Foundation IP for the creation of ASICs and SoCs for almost any process node. For over 20 years, the Nangate team, now a part of Silvaco, have been providing Foundation IP to the design community. They pride themselves in offering the best-in-class components with a full set of services which is a one-stop shop for chip developers and foundries. Read the rest of Everything You Want to Know about Silvaco Foundation IP |
