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 Silvaco Nanometer Newsbyte
Graham Bell
Graham Bell
Graham is Sr. Director of Marketing at Silvaco Inc. An experienced semiconductor-design marketing strategist and avid blogger before joining Silvaco, Graham previously was VP of marketing at Uniquify, a fabless SoC product and IP company, and at Real Intent, a verification software company. In his … More »

Webinar: Accelerating Wireless IOT SoCs with Silvaco AMBA® Subsystem IP

 
January 28th, 2021 by Graham Bell

In this webinar you will learn how Rafael Microelectronics has deployed Silvaco’s AMBA subsystem in their latest IOT design. Rafael Microelectronics develops high frequency broadband RF IC designs and narrow band IOT IP and devices. Rafael recently created a new wireless IOT SoC employing Rafael’s Bluetooth/Zigbee/Sub-GHz RF IP, leveraging Silvaco’s ABMA subsystem IP.

Rafael Microelectronics will present their requirements for the implementation of the IOT design and their adoption of the Silvaco AMBA subsystem. An overview of Rafael’s RF IP and its integration into the IOT application will be given. The ABMA Subsystem will be introduced including features such as power and memory management and system interfaces.

When: January 28, 2021
Where: Online
Time: 10:00am-10:30am-(PST)
Language: English

 Register for Webinar 

Read the rest of Webinar: Accelerating Wireless IOT SoCs with Silvaco AMBA® Subsystem IP

Customer Interview: Why I Rely on SmartSpice

 
November 18th, 2020 by Graham Bell

Martin Mallinson is an experienced analog circuit designer with multiple patents. Over his 40-year career, his audio designs have been used in millions of smartphones.  Martin spoke with Graham Bell about why SmartSpice is different from other analog simulators and how he relies on its interactivity, speed, and precision for his analog design work.

Webinar: Simulate 40X Faster with SmartSpice HPP, Nov. 17

 
November 4th, 2020 by Graham Bell

As technology advances and the complexity of circuit designs continues to grow, analog simulation can easily become the bottleneck for design verification. In order to cope with this increasing pressure on the simulator’s performance, SmartSpice provides a scalable simulation engine: HPP (High Performance Parallel). 

In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting a partition-based simulation. 

Read the rest of Webinar: Simulate 40X Faster with SmartSpice HPP, Nov. 17

Webinar: Samsung Foundry and Silvaco Design IP: The Right Solution for Your Next SoC!

 
May 13th, 2020 by Graham Bell

Samsung Foundry, a leader in advanced process, design technology, and high-volume manufacturing, has a long history of providing reliable SoC solutions with production-proven IP. Silvaco, along with its own proven IP portfolio, has been licensing and supporting Samsung Foundry IPs to SoC design teams worldwide.

In this upcoming webinar, we will provide a thorough introduction to Samsung Foundry and its process capabilities, along with the IP enablement that Silvaco provides to accelerate your design development. Silvaco will share its IP solutions optimized for high-performance computing, data centers, ML/AI applications, high speed networking, and autonomous driving platforms. In addition, interface, sensor, and security IPs for 5G and IoT systems will be presented.
Read the rest of Webinar: Samsung Foundry and Silvaco Design IP: The Right Solution for Your Next SoC!

Accelerating Design with the Victory TCAD Suite

 
March 30th, 2020 by Graham Bell

The Simulation Standard, Silvaco’s technical journal for semiconductor process and device engineers is beginning its 30th year of publication. The latest issue  has just been released and it outlines a complete power device design flow using the Victory suite of TCAD simulation solutions – Victory Process, Victory Mesh, and Victory Device. Below is an introduction to the Victory TCAD Suite article and a link the complete text which is 20 pages in length. Also in the latest issues are two Hints, Tips & Solutions articles: the first discusses handling different units in the Victory Process Material statement, and the second on “How do I Load, Remesh, and Refine an Existing Device Structure in Victory Mesh?” Click on the link to take you to the Simulation Standard article that presents all the details.

The Victory TCAD Suite

Silvaco TCAD has been used by Tier 1 power device manufactures and designers for decades. Victory Process, Victory Mesh, and Victory Device are a suite of tools that provide the functionality and flexibility that meet the needs of designers. In this article, we look at how some of the features of this suite improve the efficiency of the design flow. We go through, in detail, all the steps need to run the process, re-mesh, device, and MixedMode simulation of a trench-gated vertical IGBT.

Read the rest of Accelerating Design with the Victory TCAD Suite

TCAD Simulations of RF-SOI Switches with Trap-Rich Substrate

 
March 2nd, 2020 by Graham Bell

Four times a year, Silavco publishes its newsletter, Simulation Standard. In the most recent issue, there was an article on TCAD simulations of RF-SOI switches that use a trap-rich substrate. Below is the introduction to the article. You can read the entire article here: RFSOI Switch Harmonics Simulations with Trap-Rich Substrate.


Figure 1. Schematic cross section of the simulated RFSOI trap-rich substrate.

The market for cellular components has been shifting rapidly from GaAs pHEMT or silicon-on-sapphire (SOS) to silicon-based technology. CMOS (silicon-on-insulator) SOI antenna switches which are compatible with multimode GSM/EDGE, TD/WCDMA, and LTE systems exhibit higher integration levels and have become the fastest growing mobile phone submarket. CMOS-SOI processes, especially with thin silicon, have the potential to rival the FoM that was traditionally feasible only with GaAs technologies. This necessitates some trade-offs and optimizations of FET and substrate that need to be considered when developing a high-performance switch with high linearity and Ron*Coff < 100fs. The nonlinearity of the RF switch coming from the substrate and the active devices in terms of harmonics and intermodulation distortion could be minimized by advanced substrate and device process engineering. Advanced material engineering has been used to suppress the substrate contribution to the harmonics and intermodulation distortion. In the domain of SOI technology, it is well established that introducing a trap-rich layer compatible with both the industrial SOI wafer production and with the thermal budget of standard CMOS process at the Si/SiO2 interface is one of the most efficient techniques to overcome the problem of the substrate’s effective resistivity degradation. This degradation is due to the formation of a parasitic surface conduction (PSC) region beneath the BOX because of fixed oxide charges (Qox) within it. The trap-rich layer aims at capturing the free carriers forming the PSC and thus allowing the substrate to retain its high nominal resistivity, leading to lower losses as well as improved linearity [1-2].

In this paper, in order to understand trap-rich substrate behavior, passive and active device on SOI with trap-rich layer structures were simulated using the Victory Device simulator. Harmonics distortion of devices were also compared.

To read the complete article, click here: RFSOI Switch Harmonics Simulations with Trap-Rich Substrate.

Webinar: What’s in the New MIPI Alliance I3C V1.1 Standard?

 
February 24th, 2020 by Graham Bell

On Feb. 27, at 10am, Silvaco will be host a free webinar on “What’s in the New MIPI Alliance I3C V1.1 Standard?”  The presenter is Paul Kimelman, Platform Architect for Automotive Microcontrollers and Processors at NXP Semiconductors.

Mobile devices today contain a rich assortment of sensors that need to communicate their information as quickly as possible at the lowest possible power. To achieve this the MIPI Alliance has gathered industry leaders to create a new interface standard for connecting peripherals and sensors.

I3C has the advantages in reducing pin count, increasing performance, and decreasing power while achieving some level of backwards compatibility with the long-established I2C interface. The new I3C V1.1, announced in January 2020, enables faster interface speeds up to 100 Mhz and has many other new features that will aid the transition from I2C to I3C in applications.

Click to Register

What attendees will learn:

  • Background on the development of I3C
  • Basic MIPI I3C signaling and protocol
  • Comparison of I2C vs I3C
  • Key features of I3C
    • Lower power
    • Hot pluggable
    • High Data Rate (HDR) modes
    • Dynamic Addressing
    • In-band Interrupts
    • Common Command Codes (CCCs)
  • I3C roadmap features
  • Integrating I3C cores

Read the rest of Webinar: What’s in the New MIPI Alliance I3C V1.1 Standard?

New MIPI I3C V1.1 Standard Streamlines Peripheral Connectivity with Lower Cost and Higher Bandwidth

 
February 6th, 2020 by Graham Bell

The MIPI Alliance (MIPI) develops interface specifications for mobile and mobile-influenced industries.

There is at least one MIPI specification in every smartphone manufactured today. On January 15, MIPI announced an update to the I3C peripheral connection standard to version 1.1 with many new features. It will streamline integration and lower cost in the development of smartphones, IoT devices, server management, automotive applications, and more. MIPI I3C v1.1 is a scalable, medium-speed utility and control bus that connects peripherals to an application processor, and it is now available to MIPI Alliance members like Silvaco.

In their press release, Joel Huloux, chairman of MIPI Alliance, said “Delivering a dramatic speed increase and a host of new features to enhance reliability, MIPI I3C v1.1 significantly strengthens the upgrade path for I2C applications and enables many different use cases across mobile and multiple other markets including automotive, PC clients, data centers, drones, industrial and the Internet of Things (IoT). The specification is ideal for system-level implementers seeking a low-cost, off-the-shelf standardized utility bus solution with a small printed circuit board (PCB) footprint and a well-defined and readily available ecosystem of peripherals, sensors and applications.” Read the rest of New MIPI I3C V1.1 Standard Streamlines Peripheral Connectivity with Lower Cost and Higher Bandwidth

For Next Generation Nanowires, Simulation from Atoms to SPICE

 
January 30th, 2020 by Graham Bell

*** This blog was written by Udita Kapoor, Field Application Engineer at Silvaco ***

As process nodes continue to shrink, the requirement for additional physics-based simulation is gradually creeping into each stage of the design process. By way of illustration, Technology Computer Aided Design (TCAD) simulations are becoming more atomistic in nature, SPICE models are becoming process aware to take account of localized strain effects, and back or middle end of line (BEOL or MEOL) parasitics are moving from exclusively two-dimensional (2D) rule-based solutions to full 3D structure field solvers for numerous critical sections of the layout.

With this extra requirement for additional physics for all stages of the design flow in mind, we must have a single design interactive environment to flow seamlessly from 3D process and device physics based TCAD, to final SPICE circuit simulation including SPICE model parameter extraction from the TCAD simulations. The modularity of the flow also allows entire sections of the flow to be left out if not required. For example, if SPICE model cards are sufficiently accurate, the designer can omit the TCAD sections of the flow and concentrate on design optimization on circuit performance.

Here, a 3D atomistic to SPICE circuit simulation flow is demonstrated. It allows investigation of impact different variables of interest can have on the final circuit performance. Aspects such as process parameters, SPICE model fitting sequence, and changes in circuit configuration, can all be investigated through a single design environment. The tool flow sequence and user choices for each step are outlined in this article. The general DTCO flow is illustrated in Fig. 1. Read the rest of For Next Generation Nanowires, Simulation from Atoms to SPICE

Best Nanometer Newsbyte Blogs of 2019

 
January 23rd, 2020 by Graham Bell

As we start 2020, we can look back to 2019 and report on the blogs and articles that were most read on Silvaco’s Blog site. Topics covered were SOC design with SIPware IP, TCAD for power electronics, SPICE modeling, and atomistic device analysis.

Top Silvaco Blogs for 2019
Free 350 pg. Book on SoC Design & Secure Autonomous Driving Webinar
The Need for Advanced Wide Bandgap Power Electronics
230 Papers on Power Device Simulations using Silvaco TCAD
3D TCAD Simulation for Power Devices
Summary of the 12th International MOS-AK Workshop and Photo Gallery
Atomistic Analysis and Next Generation Computing at IEDM 2019

We also publish Nanometer Newsbyte blogs on EDACafe.com that have received thousands of views. The top stories covered Avery Design verification IP, features of SmartSpice, IP fingerprinting and DNA analysis, and foundation IP characterization.

Top EDACafe.com Blogs for 2019
Why are Silvaco and Avery Design Working Together?
SmartSpice Does It Smart
System and Method for IP Fingerprinting and IP DNA Analysis
What are the Challenges of Nanometer Library Characterization?

Read the rest of Best Nanometer Newsbyte Blogs of 2019

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