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Gabe Moretti
Gabe Moretti
Mr. Moretti’s engineering career started in July 1968 at TRW Microelectronics laboratory where he developed one of the first logic simulators for the semiconductors industry. His carrier included working at Intel, Signetics (part of Philips NV), Chancellor Computers, and VeriBest (Intergraph) … More »

DVCon US 2018 is Bigger and Better

 
February 1st, 2018 by Gabe Moretti

During the last week of February, the DoubleTree hotel in San Jose, California will once again host DVCon U.S. Dennis Brophy, this year’s General Chair, refers to DVCon U.S. as being “bigger and better”. How much longer the conference can squeeze into these premises is a challenging topic for Accellera Systems Initiative, the conference sponsor since the turn of the century.

Dennis remembers the humble beginnings of this event in 1988. To disguise his age or maybe to underlie his seniority he claims not to remember attending it, but I know he was there. Much has happened since then in our industry, and much has changed. DVCon has changed and grown with the industry and it is now a truly world-wide institution with conferences occurring also in Europe, India, and China.

DVCon has followed closely the changing realities of the electronics industry. From a place to learn about new Hardware Description Languages to one where you can attend a session about Big Data and autonomous automobiles, for example. From just three workshops presented by the leading companies in EDA to an entire day of workshops that will parallel the tutorial sessions. But let me go in order.

The Keynote Presentation
As every self-respecting conference, DVCon offers a keynote presentation. This year Christopher Tice, vice president of Verification Continuum Solutions in the Verification Group at Synopsys will deliver the keynote, “Industry’s Next Challenge: The Petacycle Challenge.” Dennis stated that: “This is the first time Mr. Tice will address DVCon. Mr. Tice is a longstanding and respected industry executive who has a focus to drive solutions in fast-growing verticals such as automotive, networking and IoT. Mr. Tice greatly complements this year’s program content and the future we look forward to creating.”

There have been discussions about the future nature of a keynote speech. It is time to think not just about tools and use methodology, but also about the nature of the problems we, as engineers, are asked to solve. It would be appropriate for a keynote to address customer industries and learn what they consider important and timely. Maybe that could be followed by a panel debating the tools and methods required. Whether they already exist and must be used in a novel way, or whether they must be invented. DVCon has been a leading learning experience for the attendees, both through the conference program and the networking opportunities offered. It may be time for the conference to also become a vessel for problem solving learning.

Accellera Day
In the last few DVCon U.S. conferences Monday has been dedicated to topics important to Accellera, the sponsoring consortium. This year there will be two workshops, one in the morning and one in the afternoon. The afternoon topic is UVM whose full name is Universal Verification Methodology. I want to spell out its full name because of what I am going to say about the morning workshop. The UVM workshop will cover the changes that the IEEE has made about standards that impact UVM and how Accellera has positively and timely reacted to help UVM users by creating a compatible reference implementation consistent with the IEEE standard (1800.2™-2017).

The morning workshop is dedicated to a developing standard that has required significant technical assets from Accellera: Portable Test and Stimulus (PTS). To say that the name of this effort is unfortunate would be only to agree with the leaders of the work, but it seems that once a name is chosen, it sticks.
The problem is that the name has generated significant confusion on the part of its future users, who are concerned about a conflict between it and UVM. I would like to point out that this upcoming standard is part of the Universal Verification Methodology and does not at all generate a conflict with UVM. In fact it completes it. PTS should have been called something like ARchitectural TEstbench DEScription (ARTEDES) and there would have been no confusion. ARTEDES is the method to be used to describe what needs to be tested while UVM allows you to specify how. Maybe it is not too late for Accellera to hold a naming contest for PTS. I will not be offended if ARTEDES does not win. No matter what the name this is an important tutorial to attend.

Technical Program
Tom Fitzpatrick, DVCon U.S. Program Chair, and his team have designed a strong program that offers Technical Papers Sessions, Posters Sessions, and Panels. The most demanding task of the Technical Program committee was deciding which papers of the many received would be accepted. It is often difficult for engineers not accustomed to speak front of an audience to deliver a well structured presentation. This year every presenter was given a tutorial on public speaking. The steering committee hopes that in this way attendees will be able to better concentrate on the contents of the presentation and struggle less with the manner in which they are presented.

During Tuesday and Wednesday there will be a total of 39 technical papers and 33 poster presentations available. The topics covered include UVM, functional and formal verification, high-level synthesis, C/C++/SystemC, assertion-based verification, Portable Stimulus, safety critical verification and ISO 26262 fault analysis, advances in low-power design and verification. As in the past, attendees will vote to choose both the best paper and the best poster in the conference.

On Tuesday evening, from 6:00-8:00 a collocated event will address formal verification with the title “Conquering Formal Verification: Go Deep or Go Broad?”

This year DVCon will offer two panel discussions and both will be held on Wednesday. The first panel reflects the issue that has come with the advent of large designs: Big Data. The greater verification information that is generated, the harder it is to find root causes to problems or system flaws. With so much information being generated, it becomes harder to attain the desired system coverage. The second panel will explore the right tool for the hardest verification jobs. The good news for design and verification engineers is that there are many tools to choose from and the panel should help understand which tool is best for which task.

The last day of DVCon has traditionally been dedicated to tutorials. This year short workshops were added to the Thursday agenda. They are meant to draw more topics to provide attendees more opportunities to join in discussions and learning exercises that would not be as long and comprehensive as full tutorials. The four Short Workshops on Thursday include topics on Deep Learning for the Design & Verification Engineer, Formal Verification, Mutation Coverage for Advanced Bug Hunting and one that will seek to have the design and verification engineer focus on getting the job done without concern that underlying it all is formal technology.
Six tutorials complete the program. The Thursday morning sessions deal with EDA tools topics covering verification speed, metric-based methodology and formal verification. The afternoon tutorials cover topics in the automotive market segment. This is a new approach by the conference intended to present requirements from specific market segments. The topics are: Making car safer, ISO26262 compliant verification, and functional safety verification for ISO 26262 requirements.

Exhibits
A month ahead of the conference, the exhibit floor is nearly sold out. Exhibitors will showcase the latest in EDA tools, design and verification IP, and services. The exhibit floor is also the place where the evening reception will take place on the first three days of the conference. Together with the sponsored luncheons these are both learning and social opportunities to interact with peers and share experiences with business connections. In front of the entrance to the exhibits area attendees will have the opportunity to stop by the ESDA (Electronics System Design Alliance) consortium table to find out what the organization focused on the business needs of the industry is doing, and maybe even become individual members of ESDA.

My Opinion
Contrary to other conferences that try to cover an increasing number of topics in an effort to attract increasing numbers of attendees and exhibitors, DVCon has remained focused on design and verification issues, and increasing, when possible, the depth of coverage of the topics. To be sure, the four days are intensive and attendees cannot afford leisure time. DVCon is about using time efficiently, getting the most for the registration price. The Steering Committee understands the investment made by each attendee in ever-increasing travel costs and the cost of being away from the day job. DVCon is sure to enrich the professional tool kit of each attendee, no matter what his or her experience level. I attend DVCon U.S. not because I love the Bay Area, but because in spite of my grey beard I still can learn a few things.

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