Mr. Moretti’s engineering career started in July 1968 at TRW Microelectronics laboratory where he developed one of the first logic simulators for the semiconductors industry. His carrier included working at Intel, Signetics (part of Philips NV), Chancellor Computers, and VeriBest (Intergraph) … More »
DVCon US 2018 is Bigger and Better
February 1st, 2018 by Gabe Moretti
During the last week of February, the DoubleTree hotel in San Jose, California will once again host DVCon U.S. Dennis Brophy, this year’s General Chair, refers to DVCon U.S. as being “bigger and better”. How much longer the conference can squeeze into these premises is a challenging topic for Accellera Systems Initiative, the conference sponsor since the turn of the century.
Dennis remembers the humble beginnings of this event in 1988. To disguise his age or maybe to underlie his seniority he claims not to remember attending it, but I know he was there. Much has happened since then in our industry, and much has changed. DVCon has changed and grown with the industry and it is now a truly world-wide institution with conferences occurring also in Europe, India, and China.
DVCon has followed closely the changing realities of the electronics industry. From a place to learn about new Hardware Description Languages to one where you can attend a session about Big Data and autonomous automobiles, for example. From just three workshops presented by the leading companies in EDA to an entire day of workshops that will parallel the tutorial sessions. But let me go in order.
The Keynote Presentation
There have been discussions about the future nature of a keynote speech. It is time to think not just about tools and use methodology, but also about the nature of the problems we, as engineers, are asked to solve. It would be appropriate for a keynote to address customer industries and learn what they consider important and timely. Maybe that could be followed by a panel debating the tools and methods required. Whether they already exist and must be used in a novel way, or whether they must be invented. DVCon has been a leading learning experience for the attendees, both through the conference program and the networking opportunities offered. It may be time for the conference to also become a vessel for problem solving learning.
The morning workshop is dedicated to a developing standard that has required significant technical assets from Accellera: Portable Test and Stimulus (PTS). To say that the name of this effort is unfortunate would be only to agree with the leaders of the work, but it seems that once a name is chosen, it sticks.
During Tuesday and Wednesday there will be a total of 39 technical papers and 33 poster presentations available. The topics covered include UVM, functional and formal verification, high-level synthesis, C/C++/SystemC, assertion-based verification, Portable Stimulus, safety critical verification and ISO 26262 fault analysis, advances in low-power design and verification. As in the past, attendees will vote to choose both the best paper and the best poster in the conference.
On Tuesday evening, from 6:00-8:00 a collocated event will address formal verification with the title “Conquering Formal Verification: Go Deep or Go Broad?”
This year DVCon will offer two panel discussions and both will be held on Wednesday. The first panel reflects the issue that has come with the advent of large designs: Big Data. The greater verification information that is generated, the harder it is to find root causes to problems or system flaws. With so much information being generated, it becomes harder to attain the desired system coverage. The second panel will explore the right tool for the hardest verification jobs. The good news for design and verification engineers is that there are many tools to choose from and the panel should help understand which tool is best for which task.
The last day of DVCon has traditionally been dedicated to tutorials. This year short workshops were added to the Thursday agenda. They are meant to draw more topics to provide attendees more opportunities to join in discussions and learning exercises that would not be as long and comprehensive as full tutorials. The four Short Workshops on Thursday include topics on Deep Learning for the Design & Verification Engineer, Formal Verification, Mutation Coverage for Advanced Bug Hunting and one that will seek to have the design and verification engineer focus on getting the job done without concern that underlying it all is formal technology.