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Archive for January, 2012

Non Volatile Memory IP for Analog and Mixed Signal Design

Wednesday, January 25th, 2012

This presentation “Non Volatile Memory IP for Analog and Mixed Signal Design” was presented at the TowerJazz Global Symposium, November 3rd at the TowerJazz headquarters in Newport Beach, California. The presenter is Bernd Stamme, Director of Marketing and Applications at Kilopass Technology Inc. in Santa Clara, California. His 20 minute presentation provides a comparison of various non-volatile memory IP (intellectual property) blocks that can be used on an integrated circuit to contain data that must be preserved when power is removed. This information might include user identification, secure codes for accessing digital rights management and others.

Cosmic Circuit’s Custom ASICs for Sensor Front Ends

Wednesday, January 11th, 2012
The January Cosmic Rays newsletter from Cosmic Circuits detailed the issues for creating custom ASICs for sensor front ends.  The article is shown here:

Custom ASICs are often deployed in sensor read-out electronics. These read-out systems tend to be unique and require the custom ASIC to

  • realize the unique functions at the power dissipation suitable for the system,
  • reduce cost and
  • protect intellectual property.

This article walks through the key elements of a custom solution for a Sensor Front End.

Successful Sensor Front Ends usually consist of the following key elements in realizing a complete solution

  1. Robust architectural definition
  2. Sensor interface electronics – often a preamplifier or instrumentation amplifier


  1. Sensor excitation circuits
  2. Calibration and Production support
Architecting the solution
Some of the key architectural decisions need to be made early in the architecture phase – these include AC or DC excitation of the sensor, , observation time of the sensor signal, voltage definition if battery operated and communication mechanism from sensor to digital processing engine.

Cosmic Circuits engineers work with customers through this phase to define an optimal solution after weighing feasibility of IC implementation.



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