Calypto has just published a new report on trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey. The survey was executed in late 2011 and had 744 SoC, IC, and FPGA design professionals respond; this report will analyze the survey results and identify relevant year-to-year trends.

By analyzing this comprehensive feedback from design engineers and engineering management, we can better understand the effort spent on reducing power consumption in the design cycle, as well as the popular low power techniques being applied. This becomes especially critical with scaling technology nodes to 65 nm and beyond.

The topics covered in this report are:

1. Survey methodology and demographics
2. Top methods used to reduce power
3. Percent of engineering time spent meeting power specifications
4. Top criteria for selecting RTL power optimization tools
5. Process nodes where RTL power optimization becomes important
6. Plans to implement power optimization tools in 2012
7. Conclusion

Click here to see the Low Power RTL Report.

In a design ecosystem increasingly influenced by software and systems development, massive verification demands, and the boundaries of physics, engineers have a wonderful new set of problems to solve! Yet the principles they will use to innovate their way to exciting solutions and products remain as fundamental and universal as the reality of the Golden Ratio itself. With the aid of some of these principles, Aart talks about what new strategies and methodologies semiconductor players will need to achieve the critical mass necessary to craft productive and creative solutions within a design ecosystem complexity that surpasses anything seen yet in human history.

Click on the graphic to view the video.

Dr. Aart de Geus CEO & Chairman of the Board Synopsys

The technical paper presentation from the Verification conference DVCon 2012 are now available online at the DVCon web-site.  You can them listed here below.

Use the BACKSPACE key to return to the main menu after drilling down into any of the sessions.

Pop-ups must be enabled to view any of the papers or slides.

The importance behind secure and fast file transfer plays a huge factor as it relates to the productivity within an engineering design workflow. Design engineers and semiconductor companies need to boost team collaboration through fast and secure content sharing around the globe to get their designs finalized and onto the chip manufacturer for creation.

Learn how to optimize the engineering design workflow and send your LARGE files faster with this new whitepaper:

Solving Engineering File Transfer Problems: Two Different Days in the Life of an Engineer

There were 8 Best Technical Paper award winners at DesignCon 2012 Jan. 30 – Feb. 2, 2012 across 5 categories.   You can see the winners for each category by clicking on the link below.

Board and System Design Category

•  “Design and Characterization of the Power Supply System for a High Speed 1600 Mbps DDR3 Interface in Wirebond Package”
• Ralf Schmitt, Rambus Inc.; Hai Lan, Rambus Inc.

High-Speed Design Category

•  “A Zero Sum Signaling Method for High Speed, Dense Parallel Bus Communications”
• Chad M. Smutzer, Mayo Clinic; Robert W. Techentin, Mayo Clinic; Michael J. Degerstrom, Mayo Clinic; Dr. Barry K. Gilbert, Mayo Clinic; Dr. Erik S. Daniel, Mayo Clinic

•  “Enhanced Equalization and Forward Error Correction Coding Technologies for 25+Gbps Serial Link System”
• Cathy Ye Liu, LSI Corporation; Pervez Aziz, LSI Corporation; Adam Healey, LSI Corporation

Interconnect Design and Test Category

•  “A Comparison of 25 Gbps NRZ & PAM-4 Modulation Used in Legacy & Premium Backplane Channels”
• Adam Healey, LSI Corporation; Chad Morgan, TE Connectivity

•  “Design Optimization for Minimal Crosstalk in Differential Interconnect”
• Beomtaek Lee, Intel Corp.; Xiaoning Ye, Intel Corp.; Raul Enriquez, Intel Corp.; Kai Xiao, Intel Corp; Ted Ballou, Intel Corp.; Jimmy A Johansson, Intel Corp.

Power and RF Design Category

•  “Are Power Planes Necessary for High Speed Signaling?”
• Suzanne L. Huh, Intel Corporation; Madhavan Swaminathan, Georgia Institute of Technology

•  “Miniaturization of Common Mode Filter Based on EBG Patch Resonance”
• Francesco de Paulis, University of L’Aquila; Bruce Archambeault, IBM;  Muhammet Hilmi Nisanci; Sam Connor, IBM; Antonio Orlandi, University of L’Aquila

Chip-Level Design Category

• “Full System Channel Co-optimization for 28Gb/s SerDes FPGA Applications with Stacked Silicon”  (no URL available)
• Namhoon Kim, Xilinx, Inc.; Daniel Wu, Xilinx, Inc.; Jack Carrel, Xilinx, Inc.; Joong-ho Kim, Xilinx, Inc.; Paul Wu, Xilinx, Inc.

Cadence Press just introduced a new title on Advanced Verification Topics by Bishnupriya Bhattacharya and contributors.  Here is a small quote from what Adam Sherer, Cadence Product Marketing Director, said in the Preface to the book:

Consumers may perceive that “it’s a digital world,” but these advanced verification topics speak to the magic that goes on under the hood of every SoC. As verification engineering managers and team leaders, we know that MDV, multi-language VIP, low-power, mixed-signal, and acceleration topics are converging at 20 nm and beyond; but we don’t want to create whole new methodologies for each one. The authors of this book realized this, and selected the Accellera UVM standard as the common base from which to offer solutions that leverage reuse and raise team-level productivity. That’s why we have written this book—not only for verification engineers familiar with the UVM and the benefits it brings to digital verification, but also for verification engineers who need to tackle these advanced tasks. Though the solutions in this book are not standardized, most of them are available through open-source code. For all of you, the material in this Advanced Verification Topics book is provided as a means to stay productive and profitable in the face of growing verification complexity.

EDACafe has exclusive previews of the text by clicking on the links below.

Advanced Verification Topics – Preface

Advanced Verification Topics – Table of Contents

Advanced Verification Topics – Ch. 5 Developing Acceleratable Universal Verification Components (UVCs)

You can also see Adam’s interview from DVCon 2012 where he introduces the book right here.

Last week was the Synopsys Users Group Silicon Valley 2012 annual meeting.   On Monday March 26, Aart de Geus, CEO of Synopsys gave an illuminating and heart felt keynote that reflected on where we have come from and where we are going as a design industry.  His mention of meeting Barney Kessel, famous Jazz guitarist, when he was a young man, poignantly told of his respect for the greatness that resides in all of us.  Afterwards, I interviewed Aart about the the keynote.

(more…)

I had the pleasure of attending the International Symposium on Quality in Electronic Design (ISQED) 2012 held in Santa Clara, March 19-21 at the Techmart.  I took some photos at the event.  See if you can spot Georgia Marsalek of ValleyPR in any of the pictures.

Enjoy!

The Common Platform Technology Forum 2012 took place at the convention center in  Santa Clara, CA on March 14th.  The Common Platform is an alliance of Samsung, IBM and GLOBALFOUNDRIES to deliver foundry services using the same silicon platform.   I had the pleasure of listening to the Keynote addresses in the morning and visit the Partner Pavilion in the afternoon to see all the ecosystem partners for the Common Platform.  Since it was “PI day” (3/14), we enjoyed pie-on-a-stick at break time between program events.   You can see what that looks like in the photo gallery below.

Follow the links to listen to each of the Keynotes:

Dr. Gary Patton, Vice President of Semiconductor Research and & Development Center, IBM spoke on  “Is Scaling Over? or Is there a Future in Silicon and Beyond?”

Subramani Kengeri, Head of Advanced Technology Architecture, Office of the CTO, GLOBALFOUNDRIES spoke on “Winning Together – Driving Innovation through Strategic Collaboration”

Dr. Jong Shik Yoon, Senior Vice President of Semiconductor R&D, Samsung spoke on “3D Device Technologies – Opportunities and Challenges”

Simon Segars, Executive Vice President and General Manager, Physical IP Division, ARM spoke on “Collaborative Scaling to 14nm and Beyond”

(more…)