Calypto has just published a new report on trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey. The survey was executed in late 2011 and had 744 SoC, IC, and FPGA design professionals respond; this report will analyze the survey results and identify relevant year-to-year trends.

By analyzing this comprehensive feedback from design engineers and engineering management, we can better understand the effort spent on reducing power consumption in the design cycle, as well as the popular low power techniques being applied. This becomes especially critical with scaling technology nodes to 65 nm and beyond.

The topics covered in this report are:

1. Survey methodology and demographics
2. Top methods used to reduce power
3. Percent of engineering time spent meeting power specifications
4. Top criteria for selecting RTL power optimization tools
5. Process nodes where RTL power optimization becomes important
6. Plans to implement power optimization tools in 2012
7. Conclusion

Click here to see the Low Power RTL Report.