There were 8 Best Technical Paper award winners at DesignCon 2012 Jan. 30 – Feb. 2, 2012 across 5 categories.   You can see the winners for each category by clicking on the link below.

Board and System Design Category

•  “Design and Characterization of the Power Supply System for a High Speed 1600 Mbps DDR3 Interface in Wirebond Package”
• Ralf Schmitt, Rambus Inc.; Hai Lan, Rambus Inc.

High-Speed Design Category

•  “A Zero Sum Signaling Method for High Speed, Dense Parallel Bus Communications”
• Chad M. Smutzer, Mayo Clinic; Robert W. Techentin, Mayo Clinic; Michael J. Degerstrom, Mayo Clinic; Dr. Barry K. Gilbert, Mayo Clinic; Dr. Erik S. Daniel, Mayo Clinic

•  “Enhanced Equalization and Forward Error Correction Coding Technologies for 25+Gbps Serial Link System”
• Cathy Ye Liu, LSI Corporation; Pervez Aziz, LSI Corporation; Adam Healey, LSI Corporation

Interconnect Design and Test Category

•  “A Comparison of 25 Gbps NRZ & PAM-4 Modulation Used in Legacy & Premium Backplane Channels”
• Adam Healey, LSI Corporation; Chad Morgan, TE Connectivity

•  “Design Optimization for Minimal Crosstalk in Differential Interconnect”
• Beomtaek Lee, Intel Corp.; Xiaoning Ye, Intel Corp.; Raul Enriquez, Intel Corp.; Kai Xiao, Intel Corp; Ted Ballou, Intel Corp.; Jimmy A Johansson, Intel Corp.

Power and RF Design Category

•  “Are Power Planes Necessary for High Speed Signaling?”
• Suzanne L. Huh, Intel Corporation; Madhavan Swaminathan, Georgia Institute of Technology

•  “Miniaturization of Common Mode Filter Based on EBG Patch Resonance”
• Francesco de Paulis, University of L’Aquila; Bruce Archambeault, IBM;  Muhammet Hilmi Nisanci; Sam Connor, IBM; Antonio Orlandi, University of L’Aquila

Chip-Level Design Category

• “Full System Channel Co-optimization for 28Gb/s SerDes FPGA Applications with Stacked Silicon”  (no URL available)
• Namhoon Kim, Xilinx, Inc.; Daniel Wu, Xilinx, Inc.; Jack Carrel, Xilinx, Inc.; Joong-ho Kim, Xilinx, Inc.; Paul Wu, Xilinx, Inc.