Embedded Software 
Colin Walls
Colin Walls has over thirty years experience in the electronics industry, largely dedicated to embedded software. A frequent presenter at conferences and seminars and author of numerous technical articles and two books on embedded software, Colin is an embedded software technologist with Mentor … More » Designing a low power CPUMay 15th, 2018 by Colin Walls
First up, please remember that I am a software guy, not a chip designer. Please read this posting with that in mind. I was chatting with someone at a conference recently and they planted an idea in my brain. I am not sure what to do with the idea, so I thought that I would exercise it here. The topic was the consideration of power consumption in embedded systems – a subject I have written about before, but this was a new angle … Until recently, low power design was simply seen as a hardware issue – just a matter of using the right electronic design to minimize power. Of late, it has become the province of software engineers, but for this to be possible, the hardware design needs to accommodate the needs of software by providing:
This is fine, but the idea proposed was that the CPU could be optimized to reduce power by careful design of its instruction set – or, to be more precise, the binary encoding of instructions. Traditionally, the binary codes of CPUs’ instruction sets have been designed using a number of bit fields, which designate the type of instruction, mode of operation, registers in use, etc. This seems logical and makes the binary code easier to analyze and understand and somewhat simplifies the instruction decoding. It is this last part which is interesting, as the simplification is not drastic. If arbitrary numbers were assigned to each unique instruction, decoding would still be reasonably straightforward. There has been no incentive to take this approach – until now. In an electronic circuit, a key factor that affects power consumption is a logic transition – 0 to 1 or vice versa. So, in theory, minimizing the number of transitions would reduce power consumption. When a CPU executes a sequence of instructions, there are logic transitions associated with the difference in the binary code of one instruction compared with the next. If the binary instruction set could be designed to minimize transitions, power consumption would be reduced. This brings us back to software, because the code determines the sequence of instructions. All that needs to be done is the analysis of a large body of typical embedded code, looking for common sequences of two or more instructions. These instructions could then be assigned values that differ in fewer bits [preferably just one]. I have no idea whether this idea is original or whether it has been deployed. Any input by comment or email would be appreciated. 4 Responses to “Designing a low power CPU” |
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Hi Colin,
Of all the things that happen in a CPU causing power consumption, the bit transitions of the instruction register are probably of minimal concern. And the increased power consumption of the more complex decoding logic would probably cancel out any possible gains.
Hi Colin, The idea you propose is not original. It was published in 1993. The idea or reducing power by reordering instructions to reduce the number of toggles in the instruction bits. Work published in 1994 (SW analysis and optz of power, by Tiwari et al) based on actual power measurements of instruction sequences showed that this made no significant difference in power consumption. Others applied the measurement based technique to other processors and came to the same conclusion. The reason is that instruction decoding is only a small fraction of the overall transistor/area/power budget of a CPU. And its only the input data path – from the Instruction Cache to the decoder (and perhaps the memory to Icache paths) where the idea above would matter. It will be swamped by power consumption from rest of the chip. If you are interested, can send out the references later. Best – Vivek Tiwari
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In an electronic circuit, a key factor that affects power consumption is a logic transition – 0 to 1