With its new ImperasDV solution, the company aims at enabling all RISC-V developers to accomplish the complex task of processor IP verification more efficiently

“The greatest migration in verification responsibility in the history of EDA,” from processor IP vendors to SoC designers: this, according to Imperas Software, is the challenge facing SoC development teams as they take advantage from RISC-V customization capabilities. One of the reasons for the success of RISC-V is undoubtedly the possibility for any SoC developer of adding some degree of customization to the basic instruction set architecture, while saving the processor compatibility with the RISC-V ecosystem of supporting tools and software. The other side of the coin, however, is a heavier verification burden on the SoC development team: as opposed to an off-the-shelf processor IP which is pre-tested by the vendor, a customized processor needs to be verified by whom performed its customization. Addressing this challenge, Imperas Software has recently launched ImperasDV, an integrated solution for RISC-V processor verification.

This new product is the main subject of the video interview that Larry Lapides, Vice-President at Imperas Software, has recently given to EDACafe’s Sanjay Gangal. In this article we will take a closer look at ImperasDV, adding a few details to the video interview content. We will also briefly discuss another major part of Imperas’ product offering, virtual platforms for embedded software development – along with the promotion of open model library availability through the Open Virtual Platforms (OVP) industry consortium. Based near Oxford, UK, with offices in Silicon Valley and Tokyo, Imperas software was founded in 2008 by Simon Davidmann, an EDA veteran.

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Achieving 5x battery life without any hardware changes: according to Deepak Shankar, Mirabilis Design’s founder, this is an example of the benefits that can be obtained through his company’s system-level architecture exploration solution, based on the VisualSim IP libraries

System-level architecture exploration is an increasingly important task for designers, especially when it comes to optimizing power or performance for complex SoC designs. Software company Mirabilis Design (Sunnyvale, CA) has chosen to address this specific area, through a system-level simulation platform – its flagship product VisualSim Architect – that employs IP libraries built in-house. In the last year and a half, the company has seen almost a 6x increase in revenue and almost a 15x jump in the number of customers (source: Mirabilis Design data), partly owing to the new remote collaboration needs brought about by the Covid-19 pandemic. Deepak Shankar, founder and Vice President of Technology at Mirabilis Design, has reiterated the key concepts of his company’s approach in the video interview he has recently given to EDACafe’s Sanjay Gangal. For this article, he has also answered a few additional questions.

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Ansys’ Matt Commens explains the new function and recaps the key features of this collaboration tool, which enables designers of high frequency systems to use accurate 3D component models specifically developed for the HFSS simulation engine

The latest Ansys release (2021 R2) includes updates to HFSS 3D Components, a tool that enables what the company calls “electromagnetic simulation collaboration” between component vendors and system integrators through the use of 3D component models specifically developed for HFSS (Ansys’ 3D high frequency electromagnetic simulation software). Matt Commens, Principal Product Manager for HFSS at Ansys, has described the key features and new functions of HFSS 3D Components in the video interview he has recently given to EDACafe’s Sanjay Gangal; in addition to that, we have asked Matt a few more questions on some specific aspects.

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Cadence’s Vinay Patwardhan explains how designers can tackle the challenges posed by 3D ICs using the new solution recently announced by the company

Placing multiple chips in a single package – either in a 2.5D or in a 3D fashion – is emerging as a viable solution to continue advancing IC performance and functionalities using the currently available process nodes, while keeping die size within lithography reticle limits. However, a package containing two or more dies can be considered as a new type of system, posing new system-level challenges. Existing EDA tools – even the most advanced ones – are mostly meant to address the challenges posed by a single chip and its package; for this reason, the EDA industry is now coming up with new solutions specifically addressing the needs of 2.5D and 3D ICs. Cadence, in particular, has recently announced a new platform called “Integrity 3D-IC”, which it describes as the “industry’s first comprehensive 3D-IC platform for multi-chiplet design and advanced packaging”. To know more about this solution, EDACAfe’s Sanjay Gangal has conducted a video interview with Vinay Patwardhan, Product Management and Group Director, Digital and Signoff Group at Cadence Design Systems.

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Called mPower, the new software fills an important gap in the EDA market, says Siemens’ Joe Davis

Smaller process geometries make electromigration (EM) and voltage drop (IR) analysis more important than ever for new chip designs, as interconnects and material layers get thinner and thinner. At the same time, smaller geometries mean skyrocketing transistor counts, making detailed EM/IR analysis of a full design a daunting task. On top of that, the growth of sensor-based applications leads to larger analog blocks, where the techniques used in digital blocks to simplify EM/IR analysis are not applicable.

Is the EDA industry keeping pace with the ever-harder requirements of power integrity analysis? According to Siemens, until yesterday the answer was no – and this resulted in some critical pain points. “The largest, most complex analog systems are often sent to manufacturing without a detailed EM/IR analysis; simplifications, subsetting the design, less accurate simulators and other ad hoc methods are used as approximations; lack of detailed EM and IR analysis for large-scale analog circuits puts the whole system at risk,” Siemens maintains in a document on this topic. Identifying those pain points as a market opportunity, Siemens is now introducing its new mPower power integrity software for analog, digital and mixed-signal IC designs. Let’s take a closer look at mPower with the help of Joe Davis – Senior Director at Calibre Interfaces, EM/IR Product Management at Siemens – who recently gave a video interview on this topic to Sanjay Gangal from EDACafe.

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The new Cerebrus Intelligent Chip Explorer recently announced by Cadence is a machine learning-based tool that automates and scales digital chip design, in combination with the Cadence RTL-to-signoff flow. It promises the ability to improve engineering productivity by up to 10X versus a manual approach while also realizing up to a 20% better power, performance and area (PPA) metrics. Rod Metcalfe, Product Management Group Director at Cadence Design Systems, has described the key features of Cerebrus in the video interview he has recently given to EDACafe’s Sanjay Gangal; in addition to that, we have asked Rod a few more questions on some specific aspects of the tool.

Key ingredients: reinforcement learning, distributed computing

As Metacalfe explained in the video interview, Cadence thinks Cerebrus will represents the future of digital chip design. “First of all – he said – we’ve developed a unique reinforcement machine learning engine that really helps optimize the full flow of a digital design. This will allow chip designers to get better PPA more quickly, so it’s going to improve the productivity of the design teams. Now, this is an automated RTL to GDS full flow optimization, and it’s based on some distributed computing technology. It can either be on-premises compute or it can be cloud resources, but the idea is really that Cerebrus is very scalable. It can adapt to the bigger designs that design teams are doing today.”

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As gate count of advanced chips gets bigger and bigger, design teams need more powerful emulation and prototyping systems to reduce time-to-market. Cadence, for its part, is responding to this need with the introduction of its Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems, the latest generation of a coordinated solution that the company has dubbed “Dynamic Duo”. Let’s now take a closer look at these two new systems with the help of Paul Cunningham, Senior Vice President, System & Verification Group at Cadence, who recently gave a video interview on this topic to Sanjay Gangal from EDACafe.

EDACafe interviews Paul Cunningham, Senior Vice President, System & Verification Group at Cadence

Doubled capacity, 50% performance increase

The key to improved performance and capacity – compared to the previous generation of these systems, Palladium Z1 and Protium X1 – is the adoption of new processing engines. “They are powered by two different chips,” Cunningham explained. “Palladium Z2 is powered by a custom ASIC we actually built here at Cadence, (…) and Protium X2 is based on a massive capacity, leading edge Xilinx FPGA, the VU19P.” As Cunningham pointed out, Cadence has built two entirely new platforms around these chips, with new rack and new boards, achieving significant results: “Within the same rack footprint [as the previous generation], we are doubling the capacity per rack and we are increasing the performance by 50%. So there’s a very significant uplift in both these platforms.”

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Selecting the right construction for a PCB stack and meeting the tight loss budget of PCB transmission lines are major challenges for designers and manufacturers of high-frequency printed circuit boards. According to Avishtech – a young San Jose-based provider of innovative EDA solutions – traditional EDA tools fall short of needs in those two areas, often leading to a trial-and-error development process that translates into long design cycles and increased costs.

Avishtech started addressing these problems in 2019. “That’s when me and my partners saw an opportunity to really make an impact and actually do things in a very different way,”, said founder and CEO Keshav Amla in the video interview he recently gave to Sanjay Gangal from EDACafe. “We had the right backgrounds and we felt that we were the right people to do that.” So after completing his master’s degree, in 2019 Amla left his PhD program to work on Avishtech full-time. One year later, in July 2020, the company launched its Gauss product line: Gauss Stack, a PCB stack-up design and simulation solution, and Gauss 2D, a field solver that improves transmission line loss modeling. Let’s now take a closer look at Avishtech and at the recently announced latest versions of its tools.

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As reported by EDACafe last July, Mentor has extended their Recon technology to the Calibre nmLVS circuit verification platform. The resulting product is called Calibre nmLVS-Recon, where LVS stands for Layout Versus Schematic, and Recon stands for reconnaissance. This week we will take a closer look at this new tool with the help of Hend Wagieh, a Senior Calibre Product Manager at Mentor, a Siemens business. In the video interview that Wagieh has recently given to Sanjay Gangal from EDACafe, a number of topics concerning Calibre nmLVS-Recon have been addressed. Wagieh set up the context by briefly recapping what Calibre is about: a comprehensive platform for design automation and design analysis, which includes a number of tools for physical verification, circuit verification, parasitic extraction, yield enhancing. According to Wagieh, Calibre is used by “twenty-three out of the top twenty-five” companies designing chips worldwide.

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Addressing the challenges of SoC integration

Ever-growing transistor count and higher complexity make System-on-Chip integration an increasingly challenging problem, still waiting for a fully satisfactory EDA solution. Connecting IP blocks – sourced either from IP vendors or from design reuse – is just the beginning of the integration process; the difficult part is reaching the best possible PPA combination within tight deadlines, while keeping engineering costs under control. One of the EDA vendors that are specifically addressing the SoC integration challenges is Defacto Technologies, a small, fast growing company based in Grenoble, France and in San Jose, California. Defacto has recently introduced a new release of its Star platform and is working on more new features to be announced at the upcoming virtual DAC. Complementing the recent EDACafe video interview, we have asked some additional questions to Chouki Aktouf, Defacto’s CEO.

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