Will “programmed logic” (that is, GPUs and deep learning accelerators) give way to “hard-wired logic” in artificial intelligence applications? Taalas, a startup recently emerged from stealth, has no doubt about that (see the news below). Meanwhile, programmed logic keeps advancing – with Cerebras doubling down on its wafer-scale approach and launching a four trillion transistor chip. Other news this week, besides Taalas, contribute to the feeling that the end of geometrical scaling won’t stop IT advancements. That includes chiplet-based solutions, of course, but also new transistor types.
Hard-wired AI models promise a 1000x improvement in computational power and efficiency
Toronto-based Taalas has recently exited stealth mode and raised $50 million dollars over two rounds of funding led by Pierre Lamond and Quiet Capital. The company’s mission is to develop an automated flow for rapidly implementing all types of deep learning models (transformers, SSMs, diffusers, MoEs, etc.) in silicon. According to the company, proprietary innovations enable one of its chips to hold an entire large AI model without requiring external memory. Taalas claims that the efficiency of hard-wired computation enables a single chip to outperform a small GPU-based data center, opening the way to a 1000x improvement in the cost of AI. “The path forward is to realize that we should not be simulating intelligence on general purpose computers, but casting intelligence directly into silicon. Implementing deep learning models in silicon is the straightest path to sustainable AI,” said Ljubisa Bajic, Taalas’ CEO. Prior to co-founding Taalas, Bajic founded Tenstorrent in 2016.
Intel outlines a UCIe-3D solution
In a paper recently published on Nature Electronics, a team of Intel researchers propose a solution for using the UCIe standard in the three-dimensional integration of chiplets. According to the authors, their architectural approach provides power, performance and reliability characteristics approaching or exceeding that of a monolithic system-on-chip design as the bump pitch approaches 1 µm. Research findings include that – contrary to trends seen in traditional signalling interfaces – the most power-efficient performance for these architectures can be achieved by reducing the frequency as the bump pitch goes down. The Intel vision is that two chiplets will connect using multiple independent modules, with each UCIe-3D PHY directly controlled by the Network-on-Chip controller. To realize this vision, the authors anticipate challenges in the areas of cooling, power delivery and reliability. Advances in electronic design automation will be necessary, too.
The U.S. government is reportedly asking the Netherlands, Germany, South Korea and Japan to put in place additional restrictions on exports to China. Japan is being asked to limit exports of chemicals such as photoresist, the Netherlands to stop ASML from servicing and repairing lithography equipment installed in China before limits on sales were put in place. Moving to this week’s news roundup, the trend towards convergence between EDA and the rest of engineering software continues – with Cadence’s acquisition of Beta CAE. Even though much smaller in financial terms ($1.24 billion), this move can be likened to the recent Synopsys’ acquisition of Ansys.
Cadence has entered into a definitive agreement to acquire Switzerland-based Beta CAE, a leading provider of structural analysis and multi-domain simulation solutions. Beta CAE has a strong presence in the automotive industry. Its flagship products include Ansa, a multidisciplinary CAE pre-processor, and Meta, a multidisciplinary CAE post-processor. Additionally, Beta CAE’s Epilysis and Fatiq solvers are used in structural analysis and optimization problems, while the SPDRM (simulation, process, data, and resources management) tool manages the CAE processes. According to Cadence, Beta CAE’s products are very complementary to Cadence’s multiphysics system analysis portfolio – which includes Clarity, Celsius, Sigrity, Voltus, Fidelity and the recently announced Millennium M1 multiphysics platform.
Altera gets its name back after eight years
Following last October decision to operate its Programmable Solutions Group as a standalone business, Intel has recently rebranded it as “Altera”. In other words, the entity is getting its original name back. Intel bought FPGA vendor Altera in 2015 and dropped its name. Now this famous brand will reappear, with the addition of “An Intel Company”. Led by CEO Sandra Rivera, Altera is now seeking additional growth opportunities in AI applications. The company has preannounced a new product series called Agilex 3 – a low-power line of FPGAs aimed at low-complexity functions for cloud, communications and intelligent edge applications. Intel plans to hold a public offering for stock in Altera over the next two to three years.
Research papers make up a large part of this week’s news roundup, some of them from the recently held ISSCC or from SPIE 2024 Advanced Lithography + Patterning Conference. But first, some updates on US and Japan’s efforts to revive their respective semiconductor industries, and some financial results.
US CHIPS Act funding applications far exceed available resources
U.S. Secretary of Commerce Gina Raimondo has recently provided some updates on the implementation of the CHIPS and Science Act. In total, applicant companies have requested more than $70 billion in federal subsidies, roughly twice the amount of funding that is available, she said. Therefore, in her conversations with chips company CEOs asking for a certain amount of funding, Raimondo tells them “You will be lucky to get half of that.” Raimondo also said the department is prioritizing projects that will be operational by 2030. U.S. Secretary of Commerce reiterated the CHIPS Act’s goal: “We think our investments in leading-edge logic chips, leading-edge logic chip manufacturing, will put this country on track to produce roughly 20% of the world’s leading-edge logic chips by the end of the decade,” she said. “Today we are at zero.”
Japan updates: TSMC, Tenstorrent
TSMC has recently held an opening ceremony for its majority-owned subsidiary Japan Advanced Semiconductor Manufacturing (JASM) in Kumamoto Prefecture, Japan. Market research firm TrendForce forecasts the plant’s total capacity to hit 40–50K wafers per month, focusing mainly on 22/28-nanometer processes with a dash of 12/16-nanometer, paving the way for the next phase of the Kumamoto expansion. The Japanese government has reportedly said it will give TSMC up to $4.86 billion more in subsidies to help it build a second chip fabrication plant in the country.
US-headquartered AI chip developer Tenstorrent has announced a partnership deal with Japan’s Leading-edge Semiconductor Technology Center (LSTC), which selected Tenstorrent’s Risc-V and chiplet IP for its edge 2-nanometer AI accelerator. In addition to the IP licensing portion of this deal, Tenstorrent will work with LSTC to co-design the chip. Under this project, Tenstorrent will also work with Japan-based Rapidus, which is planning to offer – besides chip fabrication – also advanced packaging technologies.
Market research firm TrendForce is optimistic about Japan’s chances to regain a leading position in the semiconductor industry, thanks to its equipment/material suppliers (TEL, JSR, Screen, Sumco, Shin-Etsu), availability of talent and water, a growing presence of TSMC which includes a 3D IC research center and plans for further plants.
What’s cooking at Arm after the recent, emboldening surge in its market capitalization? On the one hand, the company has unveiled two initiatives aimed at taking center stage in the emerging chiplet-based market and ecosystem. On the other hand, Masayoshi Son – CEO of SoftBank Group, the Japanese holding company that owns a 90% stake in Arm – is reportedly looking to raise up to $100 billion for a chip venture that will rival Nvidia, with a potential help from Middle Eastern investors. Should this be confirmed, some questions would arise. Why would SoftBank challenge Nvidia? After all, the surge in Arm’s market capitalization seems to be an effect of the role played by Arm CPUs in Nvidia-based AI solutions. Does SoftBank feel that the pervasiveness of Arm CPUs is an advantage position enabling it to pursue additional AI opportunities, besides Nvidia? Will Arm continue to be a pure-play, neutral IP provider, if SoftBank gets involved in a “chip venture”? As for the Middle Eastern potential investors, the report does not mention any country names, but if it were Saudi Arabia or the UAE then SoftBank would be knocking on the same doors as OpenAI’s Sam Altman – who is also reportedly hoping to raise money from investors in that geography, for his gigantic semiconductor plan. Should those investors actually agree on satisfying all these requests, the role of Middle East in semiconductor funding would become an additional geopolitical factor to consider in the context of the current “chip war”. And now, let’s move to the news.
SoftBank reportedly planning a “chip venture”
SoftBank Group’s CEO Masayoshi Son is reportedly looking to raise up to $100 billion for a chip venture that will rival Nvidia. According to the report, the project – code named Izanagi – will supply semiconductors essential for artificial intelligence. SoftBank would inject $30 billion in the project, with an additional $70 billion potentially coming from Middle Eastern institutions.
Let’s start with some comments, before getting to the news. Renesas’ acquisition of Altium will create a new, arguably unprecedented type of “bundle offer” targeted at system makers, by combining a portfolio of building blocks (chips) with a cloud-based software platform that is expected to reduce the system integration effort to put those blocks together. Will this help Renesas to sell more chips? Will this help Altium to sell more licenses? An obvious observation is that a system usually requires chips from a number of different vendors, so it’s not clear how a “privileged” relationship between a PCB design tool and just one specific chip vendor could benefit users. Unless the combined offering aims at making design system easier and more efficient for any choice of chips, including the ones that compete against Renesas products. But if this the case, it’s not clear how this could benefit Renesas. As for the impact of this acquisition on the EDA industry, it could be noted that Japan-headquartered Renesas is now directly competing against another Japanese company – Zuken – in the area of PCB design tools.
Another interesting news concerns Nvidia, reportedly building a new business unit to design bespoke chips for customers such as the hyperscalers. Waiting for more details, it can be observed that the hyperscalers internally developing their own AI chips seem to have made this decision also to gain independence from Nvidia, not just because they want tailor-made chips. In addition to that, one could ask if a new offering of bespoke GPUs could contribute to solving the GPU shortage – given the current global foundry capacity. OpenAI’s Sam Altman, who is on a mission to raise money to build new fabs, clearly thinks that the bottleneck is insufficient foundry capacity. And now, let’s move to the news.
Going public has proven to be a good choice for Arm so far. As reported by Reuters, Arm’s share price increased by more than 30% on February 7 on the strong forecast the company announced on occasion of its last quarter results. Arm’s shares are now reportedly traded at twice the price of the initial public offering. Arm’s results are part of this week’s news roundup; but first, some EDA updates.
Challenging multiphysics incumbents such as Ansys, Cadence has announced its Millennium Enterprise Multiphysics Platform, what it claims is the industry’s first hardware/software accelerated digital twin solution for multiphysics system design and analysis. The first-generation Millennium M1 accelerates high-fidelity computational fluid dynamics (CFD) simulations, mostly targeting the simulation of complex mechanical systems. Available in the cloud or on premises, this solution includes GPUs from “leading providers”, and a Cadence Fidelity CFD software stack optimized for GPU acceleration and generative AI. Millennium M1 instances can be fused into a unified cluster, enabling near-linear scalability.
The latest release from Ansys, 2024 R1, includes a new user interface and a number of other improvements. As for electronics applications, Ansys claims that this release offers significant advances in simulation performance, meshing, and automated workflows. It covers various applications such as combined chip-package-PCB simulation, RF, HPC, 3D IC, and electric motors. New capabilities include ECAD-MCAD integration in Ansys Maxwell for flex and rigid PCBs, adaptive templates in Ansys Motor-CAD, and multi-solver interoperability for multiphysics and multiscale solutions.
Confirming the growing importance of thermal aspects in electronic design, this week’s news roundup opens with two EDA announcements in this area. South Korea is also in the news with Samsung’s 3-nanometer updates and the country’s “mega cluster” plan.
Thermal design solutions from Cadence and Siemens EDA
Cadence has announcedCelsius Studio, what it claims is the industry’s first complete AI thermal design and analysis solution for electronic systems. Celsius Studio addresses thermal analysis and thermal stress for 2.5D and 3D-ICs and IC packaging, in addition to electronics cooling for PCBs and complete electronic assemblies. According to Cadence, current product offerings in the area of thermal design consist mostly of disparate point tools, whereas Celsius Studio is a unified platform that lets electrical and mechanical/thermal engineers concurrently design, analyze and optimize product performance without the need for geometry simplification, manipulation and/or translation. Celsius Studio aims at system-level thermal integrity, converging electro-thermal co-simulation, electronics cooling and thermal stress. It was made possible by Cadence’s acquisition of Future Facilities in 2022.
Siemens EDA’s latest updates to Simcenter Flotherm software for electronics cooling simulation includes the “Embeddable Boundary Condition Independent Reduced Order Model” (BCI-ROM) technology, which allows a semiconductor company to generate an accurate model that can be shared with their clients for use in downstream high-fidelity 3D thermal analysis without exposing the IC’s internal physical structure. Siemens EDA introduced BCI-ROM in this October 2023 article.
Artificial Intelligence keeps creating “circles” – that is, producing consequences that feedback on AI itself, further amplifying its impact. Besides the well-known chip performance “virtuous circle” (powerful processors enabling AI, and AI enabling even more powerful processors), another circle is looming – virtuous or vicious, depending on the point of view. It can be described as follows: chip fabs capacity enables the construction of large datacenters, and the success of AI applications fueled by large datacenters generates the demand for even larger fab capacity. Clearly, this insatiable hunger for GPUs is “virtuous” from the point of view of semiconductor sales, but can be considered “vicious” from an energy consumption standpoint. According to a CB Insights estimate, in 2024 three million operational H100 Nvidia chips – in datacenters around the world – will collectively consume almost 14 GWh, more than the whole Guatemala state (13 GWh).
Sam Altman reportedly looking to spur the construction of new fabs
According to two press reports (here and here), OpenAI’s CEO Sam Altman is trying to launch a network of new fabs to ensure his company an abundant supply of GPUs and reduce its reliance on Nvidia. Reportedly, Altman has been discussing the project with investors from United Arab Emirates and Japan’s SoftBank Group – as well as with potential foundry partners like TSMC, Intel and Samsung. OpenAI would be the new fabs’ primary customer. “Big tech” companies are the biggest buyers of Nvidia’s H100 GPUs. In a Thread post (quoted by Reuters), Mark Zuckerberg recently wrote “We’re building a massive amount of infrastructure. At the end of this year, we’ll have ~350k Nvidia H100s — and overall ~600k H100 equivalents of compute if you include other GPUs”.
Is the $35 billion deal going to change the EDA oligopoly? Is the need for better electronics-physics integration a game changer? Is EDA as a standalone industry gradually disappearing? Will Cadence look for merger opportunities?
The rumors have been confirmed: after a seven-year partnership, on January 16th Synopsys and Ansys announced that they have entered into a definitive agreement under which Synopsys will acquire Ansys for an enterprise value of approximately $35 billion. The transaction is anticipated to close in the first half of 2025. Summing up Synopsys’ 2023 revenue (approximately $6 billion) and Ansys’ 2023 revenue guidance (approximately $2 billion), the combined entity is expected to achieve a $8 billion annual income. According to the two companies, this merger is motivated by a compelling rationale: first of all, the new customer demands stemming from the complexity of today’s intelligent systems (including the chiplet trend), which require the integration of semiconductor design and simulation and analysis, in a “silicon to systems” approach that fuses electronics and physics; besides that, new growth opportunities in areas such as automotive, aerospace and industrial, where Ansys has an established presence; and the complementarity of the two companies’ respective solutions. A key role in the integration of the two organizations will be played by Rick Mahoney, currently Chief Revenue Officer in the Go-to-Market Group at Synopsys and previously Senior Vice President of Worldwide Sales, Customer Excellence, and Marketing at Ansys.
As the company announced with a post on X (Twitter), “Intel Oregon welcomes major components of ASML first shipped High-NA EUV technology to help enable the continued and relentless pursuit of Moore’s Law.” Is this new piece of equipment going to help Intel advance its “5 nodes in 4 years” program? According to SemiAnalysis, double patterning with the “traditional” EUV litho equipment (low numerical aperture) is still a better option – in terms of cost and throughput – than single patterning with the new high numerical aperture litho equipment.
Credit: Intel
Let’s now move to more news, catching up on some of the updates from the last thirty days or so.
Synopsys to reportedly buy Ansys
It looks like the EDA oligopoly is bound to always be restricted to just three big companies. According to a January 5 report from The Wall Street Journal, Synopsys is in advanced talks to acquire Ansys for around $35 billion in a stock-and-cash deal. Reportedly, the two companies are now in exclusive negotiations. Rumors started with a December 22 Reuters exclusive report revealing that Synopsys had submitted an offer to acquire multiphysics simulation specialist Ansys. While the acquisition of Ansys would be a transformative event for Synopsys, there’s no doubt that the company co-founded by Aart de Geus has a long track record of acquiring other EDA players: just take a look at this list.
