Just a quick update somewhat related to the Intel situation, before moving to this week’s news roundup. According to a Reuters report, Qualcomm has explored the possibility of acquiring portions of Intel’s design business. While being mostly interested in Intel’s client PC design business, Qualcomm would be looking at other design units as well.
Synopsys’ 40 Gbps UCIe IP
Synopsys has announced what it claims is the industry’s first complete UCIe IP solution operating at up to 40 Gbps per pin, supporting both organic substrate and high-density, advanced packaging technologies. Capabilities of the new Synopsys 40G UCIe IP solution include single reference clock; die-to-die link initialization without the need to load the firmware; test and silicon lifecycle management features; support for AXI, CHI chip-to-chip, streaming, PCI Express, and CXL; a pre-verified design reference flow.
Synopsys’ Imaging System Simulator
Synopsys has also announced ImSym (Imaging System Simulator), a virtual prototyping platform for imaging systems, encompassing lenses, sensors, and image signal processors into a comprehensive end-to-end simulation platform. Powered by CODE V and LightTools optical design software, ImSym offers a quantitative end-to-end simulation flow, thus reducing the need for physical prototypes.
After many joys, the stock exchange gave some sorrows to Nvidia on September 3 when the company’ shares reportedly lost 9.5% in what is considered “the deepest ever single-day decline in market value for a U.S. company”. In absolute terms, Nvidia lost $279 billion in market capitalization, an indication – according to some observers – that investors are becoming more cautious about AI technology.
Intel reportedly considering selling Altera
Intel’s troubles inevitably are in the spotlight this week. Let’s quickly recap some of the latest updates, based on Reuters reports. Intel CEO Pat Gelsinger and key executives are expected to present a plan in mid-September to cut unnecessary businesses and revamp capital spending. This plan could include selling Altera – but not Intel Foundry – and pausing or halting the new fab in Magdeburg, Germany. Analysts and investors think Intel will likely be removed from the Dow Jones Industrial Average index, due to the stock’s near 60% decline this year. A Republican senator has asked Gelsinger for more details on Intel’s plans to cut more than 15,000 jobs despite being set to receive nearly $20 billion from the U.S. CHIPS Act. Former Cadence CEO Lip-Bu Tan left the Intel board – where he was sitting – as he grew “frustrated by Intel’s large workforce, its approach to contract manufacturing and its risk-averse and bureaucratic culture.”
GlobalFoundry’s new partnerships
And Lip-Bu Tan gave a keynote address at this year’s GlobalFoundry Technology Summit in Santa Clara. The event was the occasion for announcing GF’s partnerships with Efficient and Finwave. US-based startup Efficient will use GF’s 22FDX process to build its ultra-low-power CPUs. The implementation will also take advantage of 22FDX’s MRAM and Adaptive Body Biasing (ABB) capabilities. According to Efficient, current general-purpose processors are over-designed for generality, with most of their energy consumed by unnecessary internal data movement and instruction control overheads. The Efficient Fabric processor architecture, instead, is based on a dataflow execution model and provides reconfigurable hardware at compile time – promising up to 99% lower DC power without compromising performance. Massachusetts-based Finwave will collaborate with GF to optimize and scale its RF GaN-on-Si enhancement-mode (E-mode) MISHEMT technology to volume production at GF’s 200mm fab in Burlington, Vermont, using the foundry’s 90RFGaN platform. Target applications include power amplifiers in future mobile phones.
Catching up on some of the August news after the summer break, let’s start by briefly recalling Intel’s disappointing second-quarter results and the company’s cost-reduction plan: Intel will cut its headcount by more than 15%, with the majority completed by the end of 2024. Consistently with the cost-reduction plan, Intel has reportedly sold its share stake in Arm. More news this week include new solutions challenging Nvidia AI dominance, just when Nvidia’s Blackwell family is experiencing issues in reaching high volume production. According to SemiAnalysis, the problems are related to the complexity of TSMC’s CoWoS-L packaging technology and insufficient capacity for this specific version of the package.
TSMC’s European joint venture holds groundbreaking ceremony
On August 20, ESMC – a joint venture between TSMC, Bosch, Infineon and NXP – held a groundbreaking ceremony for its first semiconductor fab in Dresden, Germany. When fully operational, ESMC is expected to have a monthly production capacity of 40,000 300mm wafers on TSMC’s 28/22 nanometer planar CMOS and 16/12 nanometer FinFET process technology. Total investments are expected to exceed 10 billion euros consisting of equity injection, debt borrowing, and strong support from the European Union and German government.
Fraunhofer’s Chiplet Center of Excellence
Also based in Dresden, Germany, is the Chiplet Center of Excellence (CCoE) launched by three Fraunhofer Institutes with the purpose of partnering with industry to drive forward the introduction of chiplet technology. The CCoE will initially focus on automotive applications, developing the first workflows and methods for electronics design, demonstrator construction, and the evaluation of reliability. The Fraunhofer initiative adds to the already existing “Automotive chiplet program” from Belgian technology hub imec.
Scarce supply isn’t the only issue worrying hyperscalers when it comes to relying on Nvidia GPUs: the other factor is high price. The quest for a cheaper, homegrown alternative is driving Amazon’s chip development effort, according to a Reuters report. And Nvidia’s dominant position in the AI market prompted U.S. progressive groups and Democratic Senator Elizabeth Warren to press the Department of Justice to investigate the GPU leader over competition concerns. Meanwhile, Cerebras – an Nvidia competitor – has reportedly filed for an initial public offering in the United States, in a confidential manner.
Ultra Librarian-Footprintku AI partnership
Ultra Librarian has announced a partnership with Footprintku AI aimed at bringing Footprintku AI’s technologies in Design-for-Manufacturing (DFM) processes into the Ultra Librarian CAD library. Goal of this collaboration is to provide a new on-demand DFM-aware library for companies looking to enhance and validate their libraries for DFM.
New fab updates: Amkor, SK hynix
Packaging service provider Amkorhas signed a non-binding preliminary memorandum of terms with the US Department of Commerce to receive proposed funding as part of the CHIPS and Science Act. Amkor announced in November 2023 its plans to build its first domestic OSAT (outsourced semiconductor assembly and test) facility in Peoria, Arizona. The company projects to invest approximately $2 billion and employ approximately 2,000 people at the new facility. Upon completion, this will be the largest outsourced advanced packaging and test facility in the United States. The terms include up to $400 million in proposed direct funding, and access to $200 million in proposed loans.
Memory-based neural networks and the use of “sparse AI” at the edge are two new AI approaches included in this week’s news roundup. Reasoning failures from LLMs are discussed in our Further Reading section. But first, some EDA updates.
EDA updates: DeFacto, Ansys, Keysight, Synopsys
DeFacto and Arm have developed a joint design flow for Arm-based SoCs, covering the steps from SoC design architecture and exploration down to the generation of RTL and IP-XACT design files. The flow integrates Arm IP Explorer and Defacto SoC Compiler. The generated files are fully compatible with standard RTL2GDS SoC design flows. According to DeFacto, the joint solution significantly reduces the overall design time from specification to an SoC ready for synthesis.
Ansys is collaborating with Supermicro and Nvidia to deliver turnkey hardware, enabling acceleration for Ansys multiphysics simulation solutions. According to Ansys, sizing and configuring the right hardware for multiphysics simulation is a complex task that can significantly impact performance, cost, and productivity. Turnkey, customized hardware solutions with CPUs, GPUs, interconnects, and cooling modules allow engineers to run predictively accurate simulations more efficiently. The testing process revealed accelerations ranging from 4x to 1,600x, for different Ansys tools.
Not surprisingly, several interesting updates this week regard artificial intelligence in one way or another. Among them, the news about robotic startup Skild attracts the attention on the marriage between AI and robotics, a promising perspective also from the point of view of the study of living beings. So far, AI has achieved incredible language-centric performance: AI can even emulate the skills of a semiconductor expert, just see the news about SemiKong below. But throughout evolution, language is just the latest addition to a range of other key functions that are still difficult if not impossible to artificially replicate. Motion control is definitely one of those key functions: still today, we have no idea of how we could build a robot performing like a playing kitten – a small mammal, very far away from human beings in the evolution tree. In nature, there is no such thing as a language skill without a body, and there has to be a reason for that. So focusing on motion control sounds like approaching the problem from the right side.
GlobalWafers to get CHIPS act funding
The U.S. Department of Commerce plans to provide up to $400 million under the CHIPS and Science Act to Taiwan-headquartered GlobalWafers to build and expand facilities in Sherman, Texas (to establish the first 300mm silicon wafer manufacturing facility for advanced chips in the United States) and in St. Peters, Missouri (to establish a new facility to produce 300mm silicon-on-insulator wafers). Further, GlobalWafers plans to convert a portion of its existing silicon epitaxy wafer manufacturing facility in Sherman, Texas to silicon carbide epitaxy wafer manufacturing, producing 150mm and 200mm SiC epitaxy wafers.
TSMC is now Asia’s most valuable company. Reportedly, the Taiwanese foundry has reached a trillion dollar market value. Other interesting news this week include Accenture becoming a chip design powerhouse with the addition of approximately one thousand engineers to its centers in India. But first, some EDA updates.
Siemens’ new test and analysis solution
Siemens has introduced Tessent Hi-Res Chain software, a new circuit test and analysis solution for ICs at 5-nanometers and below. As IC designs progress to more advanced nodes, they become increasingly susceptible to manufacturing variations that can create defects and slow yield ramp. At these geometries, traditional failure analysis (FA) methods can require weeks or months of laboratory effort to investigate. According to Siemens, the new Tessent Hi-Res Chain tool addresses this problem by rapidly providing transistor-level isolation for scan chain defects. By correlating design information and failure data from manufacturing tests with patterns from Tessent automatic test pattern generation (ATPG), Tessent Hi-Res Chain transforms failing test cycles into actionable insights. The solution employs layout-aware and cell-aware technology to pinpoint a defect’s most probable failure mechanism, logic location, and physical location. According to Siemens, for advanced process nodes where yield ramp heavily relies on chain diagnosis, the new software can boost diagnosis resolution by more than 1.5x, reducing the need for costly extensive failure analysis cycles.
Altair’s HyperWorks 2024
Altair has unveiled the 2024 release of its HyperWorks platform for design and simulation. According to the company, the latest release delivers significant advancements in AI-powered engineering and business, mechanical and electronics systems design, and simulation-driven design and optimization.
Google’s fifth generation Tensor G5 chip, to be installed in the next-generation smartphone Pixel 10 series, will reportedly be produced through TSMC’s 3-nanometer foundry process. If confirmed, this move will mark a shift from Google’s fourth generation Tensor G4 chip, whose productions has been entrusted to Samsung Foundry. Let’s now move to this week’s news roundup, which includes a couple of notable acquisitions.
Altair acquires Metrics, cloud-based EDA company led by Joe Costello
Metrics, a Canadian EDA company whose executive chairman is EDA veteran Joe Costello, has been acquired by Altair. Metrics has an innovative “simulation as a service” (SaaS) business model for semiconductor electronic functional simulation and design verification. According to the two companies, the Metrics digital simulator DSim, when combined with Altair’s Silicon Debug Tools, will deliver an advanced simulation environment with superior simulation and debug capabilities. The Altair-Metrics solution can run as a desktop app, on customers’ own servers, or in the cloud. Additionally, it can run very large regressions with the customer paying only for what they use. The solution supports System Verilog and VHDL RTL for digital circuits targeting ASICs and FPGAs. According to the companies, simulations can be run concurrently and at scale, removing massive amounts of time and costs from the traditional design cycle. DSim will be available through Altair One, Altair’s cloud gateway, where it will also be available for desktop download. “Customers now have a choice in design verification,” stated Altair’s CEO James R. Scapa in a press release.
While the supply of “regular” AI accelerators continues to be a hot topic – see, for example, the Reuters exclusive report on China’s ByteDance working with Broadcom to develop an advanced AI chip – the idea of building an ASIC only devoted to transformer acceleration is definitely the most fascinating news this week. But first, some EDA and IP news, which include two NoC-related announcements – a testimony of the increasing importance of the interconnect fabric in the SoC and chiplet era.
Cadence’s NoC IP
Cadence has expanded its system IP portfolio with the addition of the Janus Network-on-Chip (NoC), targeted at both complex SoCs and chiplet-based systems. According to the company, Janus NoC mitigates the routing congestion and timing issues associated with today’s complex SoC interconnects – which often don’t become apparent until physical implementation, making it difficult to achieve the PPA targets. Janus NoC leverages Cadence’s Tensilica RTL generation tools. Customers can deploy a flow that enables architectural exploration through Cadence’s portfolio of software and hardware for simulation and emulation of their NoC, and gain insights into its performance using Cadence’s System Performance Analysis tool (SPA).
Baya’s NoC IP
Startup Baya Systems has emerged from stealth mode to announce its IP portfolio designed to obtain energy-efficient data movement in complex SoCs and in chiplet-based designs. According to the company, new solutions are needed to overcome the widening gap between memory performance and the processing needs of AI, and to take out the guesswork from the design of the intelligent fabric that connects blocks in an SoC or chiplets in a multi-die design. Baya Systems’ solution includes the WeaverPro software platform that supports the SoC designer from initial specification all the way to post-silicon tuning; and the WeaveIP, that provides components to build a unified fabric. According to the company, WeaveIP has an extremely efficient, scalable transport architecture that maximizes performance and throughput, while minimizing latency, silicon footprint and power. WeaveIP also supports standard protocols.
Not surprisingly, Samsung Foundry’s recent event confirmed at least two of the trends also recently highlighted by TSMC: the adoption of backside power delivery and the development of technologies that make it possible to place an electric chip and an optical chip in the same package. A frivolous remark on process naming: contrary to Intel Foundry and TSMC, Samsung has not switched to the Angstrom unit and prefers using tenths of a nanometer, with a point (SF1.4). Probably the most surprising announcement this week comes from a Finnish startup, claiming that it can boosts the performance of any existing multicore CPU up to 100-fold. An obvious question comes to mind: why haven’t the leading CPU vendors of the world come up with a similar solution yet? We’ll try to find out as soon as we can.
Roadmap updates from the U.S. Samsung Foundry Forum
At the recent U.S. Samsung Foundry Forum, the South Korean company announced two new process nodes, SF2Z and SF4U. The company’s latest 2-nanometer process, SF2Z, incorporates optimized backside power delivery network (BSPDN) technology, enhancing PPA compared to SF2 and reducing voltage drop. Mass production of SF2Z is slated for 2027. SF4U is described as a “high-value” 4-nanometer variant that offers PPA improvements by incorporating optical shrink, with mass production scheduled for 2025. Samsung also reaffirmed that its preparations for SF1.4 (1.4-nanometer) are progressing smoothly, with performance and yield targets on track for mass production in 2027. The company emphasized the maturity of its GAA (gate-all-around) technology, which will be used to mass produce Samsung’s second-generation 3-nanometer process (SF3) in the second half of this year and the upcoming 2-nanometer process. Another highlight was the unveiling of Samsung AI Solutions, a turnkey AI platform resulting from collaborative efforts across the company’s Foundry, Memory and Advanced Package businesses, enabling a 20% improvement in total turnaround time. The company is also planning to introduce integrated, co-packaged optics (CPO) technology.
