Not surprisingly, Samsung Foundry’s recent event confirmed at least two of the trends also recently highlighted by TSMC: the adoption of backside power delivery and the development of technologies that make it possible to place an electric chip and an optical chip in the same package. A frivolous remark on process naming: contrary to Intel Foundry and TSMC, Samsung has not switched to the Angstrom unit and prefers using tenths of a nanometer, with a point (SF1.4). Probably the most surprising announcement this week comes from a Finnish startup, claiming that it can boosts the performance of any existing multicore CPU up to 100-fold. An obvious question comes to mind: why haven’t the leading CPU vendors of the world come up with a similar solution yet? We’ll try to find out as soon as we can.
Roadmap updates from the U.S. Samsung Foundry Forum
At the recent U.S. Samsung Foundry Forum, the South Korean company announced two new process nodes, SF2Z and SF4U. The company’s latest 2-nanometer process, SF2Z, incorporates optimized backside power delivery network (BSPDN) technology, enhancing PPA compared to SF2 and reducing voltage drop. Mass production of SF2Z is slated for 2027. SF4U is described as a “high-value” 4-nanometer variant that offers PPA improvements by incorporating optical shrink, with mass production scheduled for 2025. Samsung also reaffirmed that its preparations for SF1.4 (1.4-nanometer) are progressing smoothly, with performance and yield targets on track for mass production in 2027. The company emphasized the maturity of its GAA (gate-all-around) technology, which will be used to mass produce Samsung’s second-generation 3-nanometer process (SF3) in the second half of this year and the upcoming 2-nanometer process. Another highlight was the unveiling of Samsung AI Solutions, a turnkey AI platform resulting from collaborative efforts across the company’s Foundry, Memory and Advanced Package businesses, enabling a 20% improvement in total turnaround time. The company is also planning to introduce integrated, co-packaged optics (CPO) technology.
Let’s start with just a quick mention of a remarkable event in the IT world: at its recent Worldwide Developers Conference, Apple unveiled its long-awaited artificial intelligence strategy. Details of the AI innovations introduced by Apple – with a special focus on users’ privacy – can be found here. The Cupertino announcements, however, failed to impress the financial community, and Apple shares reportedly closed down nearly 2% after the event. Let’s now move to this week’s news roundup, which includes some pre-announcements concerning products that will be on display at the upcoming Design Automation Conference.
Sigasi’s shift-left approach to HDL validation
Sigasi has announced its new Visual HDL (SVH) product line, an integrated development environment that – according to the company – is able to take advantage of the shift-left methodology and give hardware designers and verification engineers better insight during the design progress. SVH enables them to manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. SVH is fully integrated with Microsoft’s Visual Studio Code; lets users move through hierarchy views and graphics that update instantaneously as they make changes in their code; and flags problems while users enter HDL code. Starting with syntax and semantics, SVH enforces coding styles as recommended by safety standards such as DO-254 or ISO 26262 and catches UVM abuses. The new IDE comprises a tiered portfolio, offering a Designer Edition, a Professional Edition, an Enterprise Edition, and a Community Edition for non-commercial uses.
Real Intent’s tool for RTL security sign-off
Real Intent has announced Sentry, a hardware security static sign-off tool to protect designs against potential security vulnerabilities. The tool allows designers and security architects to incorporate hardware security sign-off early, as part of the RTL design process. According to the company, Sentry enables early hardware security sign-off at scale – supporting a hundred million gates with fast runtimes. Sentry analyzes data movement within the hardware, ensuring all paths adhere to stringent security protocols. In a single run, the tool performs path verifications simultaneously across multiple security specifications, such as data integrity (verifying that secure data transfers between protected domains without any corruption or unauthorized access), leakage prevention (ensuring sensitive data cannot reach unauthorized domains where it could be compromised) an interference safeguarding (stopping unauthorized data from reaching and interfering with secure domains).
Some of this weeks’ news updates are coming from Computex, Taiwan’s computer expo, which this year offered speeches from a lineup of semiconductor CEOs including AMD’s Lisa Su, Nvidia’s Jensen Huang, Intel’s Pat Gelsinger, Arm’s Rene Haas, and Qualcomm’s Cristiano Amon. While Computex isn’t the only thriving show in the IT world – just think of CES or MWC – it’s interesting to notice that its American and European counterparts died years ago. Las Vegas’ Comdex was held only until 2003; Hanover’s CeBit survived until 2018.
Ansys simplifies cloud-based simulation on Azure
Ansys has launched “Ansys Access on Microsoft Azure” to enable seamless deployment of pre-configured Ansys products on Azure cloud platform infrastructure. According to the company, Ansys’ customers using their own Azure subscription with existing Ansys licenses can now benefit from a more scalable, secure, and cost-effective approach to running HPC simulations in the cloud.
As Ansys explained in a press release, there are many challenges that need to be addressed when using simulation in the cloud. These include validating on-premises workloads that have been shifted to the cloud, the ongoing work to deploy and test new virtual machines and configuring adjacent cloud-based infrastructure in a cost-effective manner. “Ansys Access on Azure” addresses these challenges by delivering pre-tested and configured Ansys applications updated with each major release and aligned to a curated set of recommended VMs and HPC infrastructure. According to Ansys, this simplifies implementation for IT departments, giving them better control over cost.
Governments around the world keep subsidizing their respective domestic semiconductor industries, with the most recent announcements coming from China and South Korea. Meanwhile, artificial intelligence is accelerating human brain research, with Google spearheading this effort. But first, a few EDA-related updates.
Siemens’ IP quality assurance solution
Siemens Digital Industries Software has introduced Solido IP Validation Suite software, an automated signoff solution for quality assurance across all design intellectual property types, including standard cells, memories and IP blocks. The suite – which includes Siemens’ Solido Crosscheck software and Solido IPdelta software – aims to shorten the time-consuming task of validating IP across all its design views such as logical, physical, electrical, timing, and power analysis contexts. It also provides version-to-version IP qualification for more predictable full-chip IP integration cycles and faster time-to-market.
Siemens’ PyTorch-to-RTL solution for AI accelerator design
Siemens Digital Industries Software has announced Catapult AI NN software for High-Level Synthesis of neural network accelerators on ASICs and SoCs. Catapult AI NN starts with a neural network description from an AI framework such as TensorFlow, PyTorch or Keras, converts it into C++ and synthesizes it into an RTL accelerator in Verilog or VHDL for implementation in silicon. Catapult AI NN brings together hls4ml, an open-source package for machine learning hardware acceleration, and Siemens’ Catapult HLS software for High-Level Synthesis. Developed in close collaboration with Fermilab, a U.S. Department of Energy Laboratory, and other leading contributors to hls4ml, Catapult AI NN enables AI experts to develop PPA-optimized accelerators for different applications without requiring them to become ASIC designers.
The European edition of TSMC’s 2024 Technology Symposium – held in Amsterdam on May 14 – allowed EDACafe to gain some additional insights on the innovations that the Taiwan-headquartered foundry first announced on April 24 at the North America edition of the event. Besides providing a roadmap of new opportunities for chipamkers and OEMs, these innovations also shed some light on the strategies that TSMC is planning to pursue over the next few years to retain its world-leading role.
TSMC’s CEO C.C. Wei on stage in Amsterdam. Credit: TSMC
Entering “the Angstrom era” with the A16 process
Among TSMC’s most notable announcements is the upcoming nanosheet-based A16 process, where A clearly stands for Angstrom. Always keeping in mind what IEEE says about process names (i.e. that today they are just marketing labels, with no connection to the real size of transistor features), it’s inevitable to compare TSMC’s A16 process with Intel’s 18A process, and the difference in numbers – 16 vs 18 – suggests that the Taiwanese foundry hopes to leapfrog competitors even in the Angstrom era. According to the figures released by TSMC, the new A16 process – in comparison to the company’s N2P – will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15-20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products. The impact of these achievements can be significant considering large datacenters, where a 20% power reduction translates into a big amount of energy in absolute terms. TSMC’s A16 process is best suited for HPC products and is planned to enter production in 2026. As for moving existing designs to the new process, 86% of standard cells can be ported directly from N2P to A16, whereas 16% need a re-optimization.
An interesting side effect of the so-called “chip war” is that, now, even large news agencies are sometimes delving quite deep into technology topics. News agency Reuters has recently assigned reverse engineering experts to tear down a Huawei phone, to find out who made the chips inside it. The two companies that performed the analysis – iFixit and TechSearch International – found that Huawei’s Pura 70 Pro contains more China-made parts than previous models, highlighting the progress China is making towards technology self-sufficiency. Chinese components found in the high-end phone include a NAND memory that was likely packaged by Huawei’s in-house chip unit HiSilicon, and a Kirin 9010 processor that is likely a slightly improved version of the chip used by Huawei’s Mate 60 series.
Synopsys to sell its Software Integrity Group
After its recent Ansys acquisition, Synopsys is now focusing on EDA by selling its non-EDA division. The company has entered into a definitive agreement with Clearlake Capital Group and Francisco Partners, two global private equity firms, for the sale of its Software Integrity Group business in a transaction with a total value of up to $2.1 billion. Upon completion of the transaction, the business will emerge as a newly independent application security testing software provider. The existing Software Integrity Group management team is expected to lead the new privately held company, whose name has not been announced yet.
Micron to get $6.1 billion CHIPS Act funding
Micron Technology and the Biden-Harris Administration have signed a non-binding Preliminary Memorandum of Terms (PMT) for $6.1 billion in funding under the U.S. CHIPS and Science Act to support planned leading-edge memory manufacturing in Idaho and New York. Construction of the new Boise fab – which will be co-located with Micron’s R&D center – started in October 2023. The Idaho fab is expected to come online and be operational in 2025, with DRAM output starting in 2026. In New York, preliminary design, field studies and permitting applications are underway for the project; construction is expected to begin in 2025, with output starting in 2028.
EDA-related updates make up most part of this week’s news roundup, with Cadence in particular introducing several new products. But first, a CHIPS Act update.
Samsung to get $6.4 billion under the US CHIPS and Science Act
The U.S. Department of Commerce and Samsung Electronics have signed a non-binding preliminary memorandum of terms to provide up to $6.4 billion in direct funding under the CHIPS and Science Act. Samsung is expected to invest more than $40 billion in the US in the coming years. The proposed investment would turn Samsung’s existing presence in Texas into a comprehensive ecosystem for the development and production of leading-edge chips, including two new leading-edge logic fabs, an R&D fab, and an advanced packaging facility in Taylor, as well as an expansion to their existing Austin facility.
Ansys’ AI-based virtual assistant
Ansys has released its AI-powered virtual assistant, AnsysGPT, built using ChatGPT technology. The virtual assistant provides responses to queries concerning Ansys products, relevant physics, and other complex engineering topics – including simulation setup. AnsysGPT captures knowledge from new public sources, including product documentation, product and engineering-related training documentation, FAQs, technical marketing materials, and public Ansys Learning Forum discussions.
Cadence’s new Palladium and Protium systems
Cadence has announced the new Palladium Z3 Emulation and Protium X3 FPGA Prototyping systems, offering more than a 2X increase in capacity and a 1.5X performance increase compared to previous-generation systems. The Palladium Z3 and Protium X3 systems scale from job sizes of 16 million gates up to 48 billion gates, so the largest SoCs can be tested as a whole rather than just partial models. The new systems are powered by the Nvidia BlueField DPU and Nvidia Quantum InfiniBand networking platforms. Congruency is maintained when transitioning between the two systems and transitioning from virtual to physical interfaces and vice versa. The Palladium Z3 system accelerates hardware verification, and through functional and interface congruency, models can be quickly brought up onto the Protium X3 system for accelerated software validation.
Unsurprisingly, most news updates this week concern artificial intelligence in one way or another, with several new processor announcements. The so-called chip war is also in the news, with CHIPS Act updates and an analysis about Huawei.
US CHIPS Act updates: TSMC, Applied Materials
US CHIPS and Science Act’s recent updates include some applicant receiving the green-light and others getting a denial, reportedly due to “overwhelming demand”. The U.S. Department of Commerce and TSMC Arizona have signed a non-binding preliminary memorandum of terms to provide up to $6.6 billion to support TSMC’s investment of more than $65 billion in three greenfield leading-edge (2-nanometer) fabs in Phoenix, Arizona. On the other hand, the CHIPS Program Office has announced that it would not move forward with its third Notice of Funding Opportunity to construct, modernize, or expand commercial R&D facilities in the United States at this time. As a consequence, US-headquartered equipment maker Applied Materials may reportedly postpone or abandon its plans to build a $4 billion research and development facility in Silicon Valley.
Datacenter processor update: Google, Meta, Intel
Two hyperscalers have recently announced new homegrown processors. Google has unveiled the Axion Processors family, its first custom Arm-based CPUs designed for the data center. Based on Neoverse V2 CPU, the new devices will be available to Google Cloud customers later this year. According to the company, Axion processors deliver instances with up to 30% better performance than the fastest general-purpose Arm-based instances available in the cloud today, up to 50% better performance and up to 60% better energy-efficiency than comparable current-generation x86-based instances.
The news about Intel Foundry takes center stage this week. Prior to summarizing the Intel announcement, here’s a short comment. Before Pat Gelsinger took office as the company’s CEO, some investors suggested Intel to adopt the fabless model, just like AMD in 2008. Gelsinger, instead, doubled down on manufacturing, announcing not just his intention to keep the fabs, but even to offer a foundry service. Intel’s decision to separate the financial reporting for the two parts of its business – foundry service VS chip sales – is probably an unavoidable step in the implementation of Gelsinger’s strategy, and will put it to the test. On the one hand, the new reporting structure will force Intel Products (the chip sales business) to correct its inefficiencies, as it will lose the convenience of easy access to internal manufacturing resources and seemingly costless design respins. On the other hand, Intel Foundry will be forced to quickly become competitive against TSMC, also because – at least officially – Intel Products will now be free to choose any other foundry instead. As of today, an unavoidable side effect of this decoupling is the public disclosure of Intel Foundry’s substantial losses. Will Intel Foundry deliver on its promise of reaching breakeven around 2027? It would be interesting to know if Intel has a plan B, and – if so – if plan B involves going fabless as an extreme option. The new financial reporting structure makes it easy to spot the lossy business within Intel (if any), and this easy spotting capability may sound like setting the stage for divestiture. A key difference from 2008, however, is the current chip war economy, with taxpayers around the world currently subsidizing their respective domestic semiconductor industries. Depending on the dose, public subsidies can offset a company’s inefficiencies and make it competitive on the market. Let’s now move to the Intel announcement and other related news.
Intel’s financial reporting structure to separate Foundry from Products
On April 2, Intel outlined a new financial reporting structure that is aligned with the company’s previously announced foundry operating model. The new reporting structure establishes a foundry relationship between Intel Foundry, the company’s manufacturing organization, and Intel Products, comprised of the company’s product business units. Beginning with the first quarter 2024, Intel will present segment results aligned to the following operating segments: Client Computing Group (CCG); Data Center and AI (DCAI); Network and Edge (NEX); Intel Foundry; Altera; Mobileye; and Other. CCG, DCAI and NEX will collectively be referred to as Intel Products; Altera, Mobileye and Other will collectively be referred to as All Other. Under this new structure, Intel Foundry will recognize revenues generated from both external foundry customers and Intel Products, as well as technology development and product manufacturing costs historically allocated to Intel Products. Instead of recognizing manufacturing costs that were previously allocated to the product operating segments, Intel Products will be charged a market-based price by Intel Foundry. Following the adoption of this new reporting structure, Intel filed a new Form 8-K containing recalculated operating segment results for the years 2023, 2022 and 2021.
Is pain a positive thing for character-building? Or is it just that humans instinctively need to find a reason to justify pain? Quite an off-topic question here – but not that much, after all, if it stems from a speech given by Nvidia CEO Jensen Huang. For his take on character-building, see the “Further reading” paragraph at the end of this week’s news roundup. But first, some on-topic technology updates.
New Synopsys announcements from SNUG Silicon Valley
Here’s a quick overview of some of the announcements Synopsys made on occasion of its recently held annual Synopsys User Group (SNUG) conference in Silicon Valley. In the area of multi-die designs, 3DSO.ai is a new AI-driven capability built natively into Synopsys 3DIC Compiler, a unified exploration-to-signoff platform. 3DSO.ai offers optimization for signal integrity, thermal integrity, and power-network design. Also targeted at multi-die designs, Synopsys Platform Architect – Multi-Die accelerates design timelines, delivering – according to the company – a six to twelve month “shift left” from RTL for the analysis of performance and power, while accounting for the interdependencies between multiple dies and allowing early partitioning decisions. Synopsys also unveiled two new hardware-assisted verification solutions: ZeBu EP2, the latest version in the ZeBu EP family of unified emulation and prototyping systems; and HAPS-100 12, Synopsys’ highest capacity and density FPGA-based prototyping system. Additionally, the company introduced Synopsys Cloud Hybridsolution, which enables users to burst from on-prem data centers to the cloud during peak needs – automatically splitting the job based on available capacity and eliminating manual data transfers. Lastly, Synopsys announced that it has completed the acquisition of Netherland-headquartered Intrinsic ID, a provider of Physical Unclonable Function (PUF) IP.
Altair to extend its meshless technology to electronics
Altair has announced the upcoming release of Altair SimSolid for electronics – promising fast, easy, and precise multi-physics scenario exploration for electronics, from chips to PCBs and full system design. SimSolid is an already existing Altair product, which so far has gained adoption in industries such as aerospace and automotive. According to the company, SimSolid’s main benefit is its ability to eliminate geometry simplification and meshing, the two most time-consuming and expertise-intensive tasks done in traditional finite element analysis. As a result, it is up to 25x faster than traditional finite element solvers, and effortlessly handles complex assemblies. Extending Altair SimSolid’s meshless technology to electronics will enable the tool to tackle intricate challenges like signal integrity, power integrity, and electromagnetic compatibility/interference, all while making simulations more accessible and efficient.
