40 Gbps UCIe IP; 300-mm GaN wafers; new edge AI SoCs; new US export controls

Just a quick update somewhat related to the Intel situation, before moving to this week’s news roundup. According to a Reuters report, Qualcomm has explored the possibility of acquiring portions of Intel’s design business. While being mostly interested in Intel’s client PC design business, Qualcomm would be looking at other design units as well.

Synopsys’ 40 Gbps UCIe IP

Synopsys has announced what it claims is the industry’s first complete UCIe IP solution operating at up to 40 Gbps per pin, supporting both organic substrate and high-density, advanced packaging technologies. Capabilities of the new Synopsys 40G UCIe IP solution include single reference clock; die-to-die link initialization without the need to load the firmware; test and silicon lifecycle management features; support for AXI, CHI chip-to-chip, streaming, PCI Express, and CXL; a pre-verified design reference flow.

Synopsys’ Imaging System Simulator

Synopsys has also announced ImSym (Imaging System Simulator), a virtual prototyping platform for imaging systems, encompassing lenses, sensors, and image signal processors into a comprehensive end-to-end simulation platform. Powered by CODE V and LightTools optical design software, ImSym offers a quantitative end-to-end simulation flow, thus reducing the need for physical prototypes.

Infineon pioneers 300-mm GaN wafers

Infineon has succeeded in developing the world’s first 300-millimeter power gallium nitride (GaN) wafer technology. The Germany-headquartered firm has achieved this result on a pilot line in existing 300-millimeter silicon production in its power fab in Villach, Austria. According to Infineon, a significant advantage of 300-millimeter GaN technology is that it can utilize existing 300-millimeter silicon manufacturing equipment, since gallium nitride and silicon are very similar in manufacturing processes. Infineon’s existing high-volume silicon 300-millimeter production lines are ideal to pilot reliable GaN technology, allowing accelerated implementation and efficient use of capital. Infineon maintains that fully scaled 300-millimeter GaN production will contribute to GaN cost parity with silicon on R_DS(on) level, which means cost parity for comparable Si and GaN products.

Samsung Electronics to reportedly cut workforce

Samsung Electronics is reportedly cutting up to 30% of its overseas staff at some divisions. According to the press report, the South Korean company has instructed subsidiaries worldwide to reduce sales and marketing staff by about 15% and the administrative staff by up to 30%. No details have been disclosed as for the overall number of slashed jobs or which countries and business units would be most affected.

HBM4 Memory Controller IP from Rambus

Rambus has announced the industry’s first HBM4 Memory Controller IP. Supporting the JEDEC Spec of 6.4 Gigabits per second and reaching up to 10 Gbps, the new IP provides a throughput of 2.56 Terabytes per second to each memory device. The Rambus HBM4 Controller IP can be paired with third-party or customer PHY solutions to instantiate a complete HBM4 memory subsystem. According to Rambus, the controller delivers more than double the throughput of HBM3 at low latency to meet the demands of Generative AI & High-Performance Computing workloads.

Edge AI updates: SiMa.ai, Mobilint

SiMa.ai has announced Modalix, its second-generation machine-learning SoC, which – according to the company – is the industry’s first multi-modal edge AI product family. Modalix supports CNNs, Transformers, LLMs, LMMs and Gen AI at the edge, and promises more than 10X the performance per watt of alternatives. Modalix is offered in 25, 50, 100 and 200 TOPS configurations.

South Korea-headquartered Mobilint has recently unveiled Regulus, its new standalone AI SoC designed to deliver AI computing performance of over 10 TOPS while consuming less than 3W of power. It integrates high-performance CPU, codec, and ISP components, making it suitable for applications in robotics, drones, home appliances, dash cameras, and CCTV systems.

New BCD process

SK keyfoundry, an 8-inch pure-play foundry in Korea, has launched its fourth-generation 0.18-micron BCD process, which delivers approximately 20% performance improvement over the previous third-generation. The new process offers power devices up to 40V with various power device gate inputs such as 3.3V, 5V, and 18V, which can be used in a variety of applications such as PMIC for servers and laptops, PMIC for DDR5 memory, mobile chargers, audio amplifiers, and automotive gate drivers meeting AEC-Q100 Grade 1 quality standard.

Chip war updates

The U.S. Commerce Department’s Bureau of Industry and Security (BIS) has implemented new worldwide export controls on quantum computing Items, advanced semiconductor manufacturing equipment, Gate All-Around FET technology, and additive manufacturing items. Several like-minded countries have already announced or implemented new national controls for export of the same items, and BIS anticipates additional countries will implement similar controls soon.

Netherland-headquartered ASML has released a statement on an updated license requirement recently published by the Dutch government, regarding the export of immersion DUV semiconductor equipment. ASML believes this requirement will harmonize the approach for issuing export licenses. From now on, ASML will need to apply for export licenses with the Dutch government rather than the US government for shipments of its Twinscan NXT:1970i and 1980i DUV immersion lithography systems. The Dutch export license requirement is already in place for the Twinscan NXT:2000i and subsequent DUV immersion systems. Sales of ASML’s EUV systems are also subject to license requirements.

Acquisitions

Dover – a diversified global manufacturer and solutions provider headquartered in Downers Grove, Illinois – has acquired Criteria Labs, a supplier of radio frequency device and microelectronic engineering solutions for high-reliability applications in the space, aerospace, defense, commercial semiconductor, automotive, and medical industries. Criteria Lab’s locations are in Austin, Texas, and in Penrose, Colorado.

Further reading

French research institute CEA-Leti has recently presented its 3D packaging developments aimed at achieving 3-layer stacking integration for future smart imagers. Three-layer integration is particularly interesting because, in addition to allowing separate optimization of the individual layers, it also makes it possible to envisage the direct implementation of a neural network and memory, to build artificial intelligence into the sensor itself. The technology described in the article involves wafer-to-wafer hybrid bonding and high-density Through Silicon Vias, with a challenging 10:1 aspect ratio. The work was carried out in collaboration with the other partners of the IRT Smart Imager Program: STMicroelectronics, Siemens EDA, Prophesee, Lynred, Grenoble INP-UGA.

Credit: IRT Nanoelec

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