Intel’s troubles; GF’s new partnerships; PSS 3.0; new Risc-V startup; future of DRAM

After many joys, the stock exchange gave some sorrows to Nvidia on September 3 when the company’ shares reportedly lost 9.5% in what is considered “the deepest ever single-day decline in market value for a U.S. company”. In absolute terms, Nvidia lost $279 billion in market capitalization, an indication – according to some observers – that investors are becoming more cautious about AI technology.

Intel reportedly considering selling Altera

Intel’s troubles inevitably are in the spotlight this week. Let’s quickly recap some of the latest updates, based on Reuters reports. Intel CEO Pat Gelsinger and key executives are expected to present a plan in mid-September to cut unnecessary businesses and revamp capital spending. This plan could include selling Altera – but not Intel Foundry – and pausing or halting the new fab in Magdeburg, Germany. Analysts and investors think Intel will likely be removed from the Dow Jones Industrial Average index, due to the stock’s near 60% decline this year. A Republican senator has asked Gelsinger for more details on Intel’s plans to cut more than 15,000 jobs despite being set to receive nearly $20 billion from the U.S. CHIPS Act. Former Cadence CEO Lip-Bu Tan left the Intel board – where he was sitting – as he grew “frustrated by Intel’s large workforce, its approach to contract manufacturing and its risk-averse and bureaucratic culture.”

GlobalFoundry’s new partnerships

And Lip-Bu Tan gave a keynote address at this year’s GlobalFoundry Technology Summit in Santa Clara. The event was the occasion for announcing GF’s partnerships with Efficient and Finwave. US-based startup Efficient will use GF’s 22FDX process to build its ultra-low-power CPUs. The implementation will also take advantage of 22FDX’s MRAM and Adaptive Body Biasing (ABB) capabilities. According to Efficient, current general-purpose processors are over-designed for generality, with most of their energy consumed by unnecessary internal data movement and instruction control overheads. The Efficient Fabric processor architecture, instead, is based on a dataflow execution model and provides reconfigurable hardware at compile time – promising up to 99% lower DC power without compromising performance. Massachusetts-based Finwave will collaborate with GF to optimize and scale its RF GaN-on-Si enhancement-mode (E-mode) MISHEMT technology to volume production at GF’s 200mm fab in Burlington, Vermont, using the foundry’s 90RFGaN platform. Target applications include power amplifiers in future mobile phones.

EDA updates: Synopsys, Nvidia, Accellera, Celus

At the recent Hot Chips conference, Synopsys discussed the impact of the second wave of AI on chip design, with generative models now coming into play. Synopsys has also expanded the ZeBu Cloud service in its U.S. data center to offer 3X more capacity, and has established a data center certified to host ZeBu Cloud services in The Netherlands.

Nvidia, too, discussed EDA-related themes at Hot Chips, including its work on “Large Language Model (LLM) for Standard Cell Layout Design Optimization”, which won best paper at the first IEEE International Workshop on LLM-Aided Design.

Accellera’s Board of Directors has approved the Portable Test and Stimulus Standard (PSS) 3.0, which is available for immediate download. The most substantial feature added to PSS 3.0 is support for behavioral coverage where several scenarios can be generated from a single PSS specification. Accellera offers a video tutorial about “Efficient Portable Programming-Sequence Development with PSS”.

Celus – based in Munich, Germany – has added a U.S. office in Austin, Texas. The company’s AI-assisted PCB design platform promises to streamline the design process by providing “real-time component recommendations that work”. The platform’s deliverables include architectural design, ECAD native schematics, bill of materials, footprints and project information summary.

Former Intel architects found Risc-V startup AheadComputing

Last week we reported about Akeana, a startup developing a wide range of Risc-V-based processors IP. This week it’s the turn of AheadComputing, another Risc-V IP startup. Interestingly, AheadComputing was founded by four former Intel CPU architects: Dr. Debbie Marr, Jonathan Pearce, Dr. Srikanth Srinivasan, Mark Dechene. The company is based in Portland, Oregon.

Carmakers fearing China retaliation for “chip war”

The United States would probably achieve better results in the so-called “chip war” against China if China wasn’t so important for German and Japanese carmakers. Last July we reported about a study maintaining that Germany is defying US calls to cut China out of semiconductor supply chains because automotive companies depend on Chinese markets and suppliers. Now the press is reporting that China has warned Japan of severe economic retaliation if it further restricts sales and servicing of chipmaking equipment to Chinese firms. According to the report, Toyota Motor privately told Japanese officials that Beijing could react to the curbs by cutting Japan’s access to minerals required for automotive production.

SK hynix’s new memories

SK hynix has developed the industry’s first 16Gb DDR5 built using its 1c node, the sixth generation of the 10-nanometer process. The operating speed of the 1c DDR5, expected to be adopted for high-performance data centers, is improved by 11% from the previous generation, to 8Gbps. Power efficiency is also improved by more than 9%. The company said it will be ready for mass production of the 1c DDR5 within the year to start volume shipment next year. SK Hynix also reportedly unveiled il will start mass production of HBM3E 12-layer chips by the end of this month.

Further reading

Speaking of memories, a recent SemiAnalysis post addresses the fact that “DRAM doesn’t scale anymore.” According to the analysts, “In the glory days, memory bit density doubled every 18 months – outpacing even logic. That translates to just over 100x density increase every decade. But in this last decade, scaling has slowed so much that density has increased just 2x.” In terms of manufacturing, scaling challenges pointed out by SemiAnalysis are in the capacitors and sense amplifiers. Further limitations are due to the old-style DRAM architecture, with interfaces preventing to exploit the full performance potential of DRAM banks.

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