Memory-based neural networks and the use of “sparse AI” at the edge are two new AI approaches included in this week’s news roundup. Reasoning failures from LLMs are discussed in our Further Reading section. But first, some EDA updates.
EDA updates: DeFacto, Ansys, Keysight, Synopsys
DeFacto and Arm have developed a joint design flow for Arm-based SoCs, covering the steps from SoC design architecture and exploration down to the generation of RTL and IP-XACT design files. The flow integrates Arm IP Explorer and Defacto SoC Compiler. The generated files are fully compatible with standard RTL2GDS SoC design flows. According to DeFacto, the joint solution significantly reduces the overall design time from specification to an SoC ready for synthesis.
Ansys is collaborating with Supermicro and Nvidia to deliver turnkey hardware, enabling acceleration for Ansys multiphysics simulation solutions. According to Ansys, sizing and configuring the right hardware for multiphysics simulation is a complex task that can significantly impact performance, cost, and productivity. Turnkey, customized hardware solutions with CPUs, GPUs, interconnects, and cooling modules allow engineers to run predictively accurate simulations more efficiently. The testing process revealed accelerations ranging from 4x to 1,600x, for different Ansys tools.
