TSMC is now Asia’s most valuable company. Reportedly, the Taiwanese foundry has reached a trillion dollar market value. Other interesting news this week include Accenture becoming a chip design powerhouse with the addition of approximately one thousand engineers to its centers in India. But first, some EDA updates.
Siemens’ new test and analysis solution
Siemens has introduced Tessent Hi-Res Chain software, a new circuit test and analysis solution for ICs at 5-nanometers and below. As IC designs progress to more advanced nodes, they become increasingly susceptible to manufacturing variations that can create defects and slow yield ramp. At these geometries, traditional failure analysis (FA) methods can require weeks or months of laboratory effort to investigate. According to Siemens, the new Tessent Hi-Res Chain tool addresses this problem by rapidly providing transistor-level isolation for scan chain defects. By correlating design information and failure data from manufacturing tests with patterns from Tessent automatic test pattern generation (ATPG), Tessent Hi-Res Chain transforms failing test cycles into actionable insights. The solution employs layout-aware and cell-aware technology to pinpoint a defect’s most probable failure mechanism, logic location, and physical location. According to Siemens, for advanced process nodes where yield ramp heavily relies on chain diagnosis, the new software can boost diagnosis resolution by more than 1.5x, reducing the need for costly extensive failure analysis cycles.
Altair’s HyperWorks 2024
Altair has unveiled the 2024 release of its HyperWorks platform for design and simulation. According to the company, the latest release delivers significant advancements in AI-powered engineering and business, mechanical and electronics systems design, and simulation-driven design and optimization.
