Transformer-specialized ASIC; new NoC IP solutions; formal verification for C++ designs

While the supply of “regular” AI accelerators continues to be a hot topic – see, for example, the Reuters exclusive report on China’s ByteDance working with Broadcom to develop an advanced AI chip – the idea of building an ASIC only devoted to transformer acceleration is definitely the most fascinating news this week. But first, some EDA and IP news, which include two NoC-related announcements – a testimony of the increasing importance of the interconnect fabric in the SoC and chiplet era.

Cadence’s NoC IP

Cadence has expanded its system IP portfolio with the addition of the Janus Network-on-Chip (NoC), targeted at both complex SoCs and chiplet-based systems. According to the company, Janus NoC mitigates the routing congestion and timing issues associated with today’s complex SoC interconnects – which often don’t become apparent until physical implementation, making it difficult to achieve the PPA targets. Janus NoC leverages Cadence’s Tensilica RTL generation tools. Customers can deploy a flow that enables architectural exploration through Cadence’s portfolio of software and hardware for simulation and emulation of their NoC, and gain insights into its performance using Cadence’s System Performance Analysis tool (SPA).

Baya’s NoC IP

Startup Baya Systems has emerged from stealth mode to announce its IP portfolio designed to obtain energy-efficient data movement in complex SoCs and in chiplet-based designs. According to the company, new solutions are needed to overcome the widening gap between memory performance and the processing needs of AI, and to take out the guesswork from the design of the intelligent fabric that connects blocks in an SoC or chiplets in a multi-die design. Baya Systems’ solution includes the WeaverPro software platform that supports the SoC designer from initial specification all the way to post-silicon tuning; and the WeaveIP, that provides components to build a unified fabric. According to the company, WeaveIP has an extremely efficient, scalable transport architecture that maximizes performance and throughput, while minimizing latency, silicon footprint and power. WeaveIP also supports standard protocols.

Baya Systems has also recently announced a partnership with Blue Cheetah to offer a combined chiplet-optimized Network on Chip (NoC) and Physical Layer (PHY) interconnect IP solution.

Siemens’ formal verification for C++ designs

Siemens has announced two breakthrough capabilities for high-level verification of C++ for hardware design: formal property checking and reachability coverage analysis. Designed to be used with Siemens’ Catapult software for high-level synthesis and verification, the new tools – Catapult Formal Assert and Catapult Formal CoverCheck – uniquely bring known and trusted formal verification methods from the RTL world to high-level design.

Siemens’ ESD solution  

Siemens has announced a fully automated solution to rapidly identify and address Electrostatic Discharge (ESD) issues in complex IC designs, checking compliance against foundry rules regardless of targeted process technology. The solution combines Calibre PERC software with the SPICE accuracy of AI-powered Solido Simulation Suite. According to Siemens, foundry ESD rules may be overly conservative for specific design styles and mission profiles, so identifying and simulating the real critical ESD paths may help achieve better PPA.

Accellera’s Federated Simulation Standard initiative

Accellera has announced the formation of the Federated Simulation Standard (FSS) Working Group to establish cross-industry collaboration to improve the interoperability of product and environment simulation, models, and components. As Accellera explained, there are many different simulation approaches and standards from multiple industries such as avionics, space, semiconductor, automotive, and mechatronics. The goal of the new group is to leverage and connect existing industry standards and formats to facilitate modeling, integration, and simulation of complex systems and systems-of-systems. The need for a cross-industry federated simulation ecosystem is increasingly important because of the diverse companies in supply chains that are sharing and integrating more diverse models, simulators, and components.

Etched’s ASIC for AI transformer models promises 20x performance than Nvidia H100

A San Francisco startup called Etched is building Sohu, the world’s first specialized chip (ASIC) for AI transformers models, such as – for example – ChatGPT. According to Etched, over the past few years the AI industry has converged on just one single model architecture: transformers. OpenAI’s GPT-family, Google’s PaLM, Facebook’s LLaMa, and even Tesla FSD are all transformers and similar to one another. And the one and only trick for transformer advancement is scaling – that is, building ever larger models, requiring ever larger computing power. But GPUs are hitting a wall: first, because they haven’t gotten better, they’ve just gotten bigger. The compute (TFLOPS) per area of the chip has been nearly flat for four years. Second, because GPUs need to support all kinds of AI models, including CNNs, LSTMs, SSMs, and others, and therefore the vast majority of a GPU’s area is devoted to programmability. According to Etched, only 3.3% of the transistors on an Nvidia H100 GPU are used for matrix multiplication, which is the key math operation for AI acceleration. In contrast, by supporting only transformers, the Sohu ASIC is more that twenty times faster than a H100, and therefore one 8xSohu server replaces 160 H100 GPUs. Etched has partnered directly with TSMC on their 4-nanometer process. The company also said it has secured enough HBM and server supply from top vendors to quickly ramp its first year of production, and its early customers have reserved tens of millions of dollars of its hardware. Etched claims “If we’re right, Sohu will change the world,” by making AI models 20x faster and cheaper overnight.

Orca’s analog offer promises personalization and better support

Startup Orca Semiconductor has recently emerged out of stealth mode claiming to be the first analog semiconductor provider to deliver the personalization and high-level support, demanded by customers, that “Big Analog” are neglecting. Orca also announced it is sampling its first product, the OS1000, described as “the most advanced” PMIC (power management integrated circuit) in its class developed for health wearables, hearables and other connected devices.

New fab updates: Vanguard-NXP, onsemi, Silicon Box

Vanguard and NXP are planning to create a manufacturing joint-venture called VisionPower Semiconductor Manufacturing Company (“VSMC”) which will build a new 300mm semiconductor wafer manufacturing facility in Singapore. The joint venture will begin construction of the initial phase of the wafer fab in the second half of 2024, with initial production available during 2027. Onsemi is planning to establish a state-of-the-art, vertically integrated silicon carbide (SiC) manufacturing facility in the Czech Republic, with a planned multi-year investment of up to $2 billion. Vertical integration means bringing also advanced packaging capabilities to the region. Singapore-based Silicon Box is reportedly planning to pick the town of Novara for its new multibillion-euro chiplet fab in Italy. Despite belonging to a different region (Piedmont), Novara can be considered part of the greater Milan area.

Further reading

A study from think tank Rhodium Group takes a fresh look at the data on China’s legacy chip production capacity expansion after two big waves of US-led chip controls. The report then distills the theories of harm circulating in the US to outline the most likely policy pathways for the US to target China-sourced legacy chips and evaluate potential gaps between the US and G7 partners in shaping a response.

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