While the supply of “regular” AI accelerators continues to be a hot topic – see, for example, the Reuters exclusive report on China’s ByteDance working with Broadcom to develop an advanced AI chip – the idea of building an ASIC only devoted to transformer acceleration is definitely the most fascinating news this week. But first, some EDA and IP news, which include two NoC-related announcements – a testimony of the increasing importance of the interconnect fabric in the SoC and chiplet era.
Cadence’s NoC IP
Cadence has expanded its system IP portfolio with the addition of the Janus Network-on-Chip (NoC), targeted at both complex SoCs and chiplet-based systems. According to the company, Janus NoC mitigates the routing congestion and timing issues associated with today’s complex SoC interconnects – which often don’t become apparent until physical implementation, making it difficult to achieve the PPA targets. Janus NoC leverages Cadence’s Tensilica RTL generation tools. Customers can deploy a flow that enables architectural exploration through Cadence’s portfolio of software and hardware for simulation and emulation of their NoC, and gain insights into its performance using Cadence’s System Performance Analysis tool (SPA).
Baya’s NoC IP
Startup Baya Systems has emerged from stealth mode to announce its IP portfolio designed to obtain energy-efficient data movement in complex SoCs and in chiplet-based designs. According to the company, new solutions are needed to overcome the widening gap between memory performance and the processing needs of AI, and to take out the guesswork from the design of the intelligent fabric that connects blocks in an SoC or chiplets in a multi-die design. Baya Systems’ solution includes the WeaverPro software platform that supports the SoC designer from initial specification all the way to post-silicon tuning; and the WeaveIP, that provides components to build a unified fabric. According to the company, WeaveIP has an extremely efficient, scalable transport architecture that maximizes performance and throughput, while minimizing latency, silicon footprint and power. WeaveIP also supports standard protocols.
