Cadence acquires Beta CAE; Altera gets its name back; EDA standard updates; ChatGPT-generated Verilog code

The U.S. government is reportedly asking the Netherlands, Germany, South Korea and Japan to put in place additional restrictions on exports to China. Japan is being asked to limit exports of chemicals such as photoresist, the Netherlands to stop ASML from servicing and repairing lithography equipment installed in China before limits on sales were put in place. Moving to this week’s news roundup, the trend towards convergence between EDA and the rest of engineering software continues – with Cadence’s acquisition of Beta CAE. Even though much smaller in financial terms ($1.24 billion), this move can be likened to the recent Synopsys’ acquisition of Ansys.

Cadence acquires structural analysis tool vendor Beta CAE

Cadence has entered into a definitive agreement to acquire Switzerland-based Beta CAE, a leading provider of structural analysis and multi-domain simulation solutions. Beta CAE has a strong presence in the automotive industry. Its flagship products include Ansa, a multidisciplinary CAE pre-processor, and Meta, a multidisciplinary CAE post-processor. Additionally, Beta CAE’s Epilysis and Fatiq solvers are used in structural analysis and optimization problems, while the SPDRM (simulation, process, data, and resources management) tool manages the CAE processes. According to Cadence, Beta CAE’s products are very complementary to Cadence’s multiphysics system analysis portfolio – which includes Clarity, Celsius, Sigrity, Voltus, Fidelity and the recently announced Millennium M1 multiphysics platform.

Altera gets its name back after eight years

Following last October decision to operate its Programmable Solutions Group as a standalone business, Intel has recently rebranded it as “Altera”. In other words, the entity is getting its original name back. Intel bought FPGA vendor Altera in 2015 and dropped its name. Now this famous brand will reappear, with the addition of “An Intel Company”. Led by CEO Sandra Rivera, Altera is now seeking additional growth opportunities in AI applications. The company has preannounced a new product series called Agilex 3 – a low-power line of FPGAs aimed at low-complexity functions for cloud, communications and intelligent edge applications. Intel plans to hold a public offering for stock in Altera over the next two to three years.

AMD is also targeting power-sensitive edge applications with its new Spartan UltraScale+ FPGA family, the newest addition to the company’s portfolio of cost-optimized FPGAs and adaptive SoCs. According to AMD, Spartan UltraScale+ devices offer the industry’s highest ‘I/O-to-logic cell’ ratio in FPGAs built in 28nm and lower process technology, deliver up to 30 percent lower total power consumption versus the previous generation, and contain the most robust set of security features in the AMD cost-optimized portfolio.

EDA standard updates: Accellera, Si2

Accellera has announced that the recently published IEEE 1800-2023 standard for SystemVerilog is now available for download without charge, as part of the IEEE GET Program. Accellera has also announced the release of the Verilog-AMS 2023 standard, which – in response to feedback from the community – introduces enhancements to analog constructs and clarifications for existing constructs.

The Silicon Integration Initiative Compact Model Coalition (CMC) has released a new version of the Open Model Interface (OMI), an Si2 standard, C-language application programming interface that supports SPICE compact model extensions. OMI allows circuit designers to simulate and analyze physical effects such as self-heating and aging, and perform extended design optimizations. It is based on TMI2, the TSMC Model Interface, which was donated to Si2 by TSMC in 2014. OMI supports twelve of CMC’s fifteen SPICE models. This is the first release of OMI to also support non-MOSFET devices.

IP updates: Cadence, Synopsys

Cadence has expanded its Tensilica IP portfolio to address the increasing computational requirements associated with automotive sensor fusion applications. The new Tensilica Vision 331 DSP and Vision 341 DSP combine vision, radar, lidar and AI processing in a single DSP for multi-modal, sensor-based system designs, improving energy efficiency and area. This DSP IP can be paired with the new Cadence Tensilica Vision 4DR Accelerator optimized for 4D imaging radar applications.

Synopsys has introduced what it claims is the industry’s first complete 1.6T Ethernet IP solution, aimed at hyperscale data centers.

Applied Materials’ patterning innovations

At the recently held SPIE Advanced Lithography + Patterning conference, Applied Materials introduced new patterning products and solutions. The Sculpta patterning system, which allows to reduce EUV double patterning steps by elongating patterned features, can now be used for new applications in addition to reducing tip-to-tip spacing: for example, to remove bridge defects. The Sym3 Y Magnum etch system, which combines deposition and etch technology in the same chamber, deposits material along rough edges, making EUV line patterns smoother before they are etched into the wafer. This enables an increase in yields and a decrease in line resistance. The Producer XP Pioneer CVD (chemical vapor deposition)​ patterning film is deposited on the wafer prior to photoresist pattern processing and is designed to transfer desired patterns to the wafer with fidelity. Lastly, contour technology from recently acquired Aselta Nanographics is now being integrated with Applied’s VeritySEM CD-SEM system and PROVision eBeam metrology system, to avoid placement errors.

Using ChatGPT to generate the Verilog design of a neuromorphic chip

A research team from Johns Hopkins University (Baltimore, MD) has succeeded in having ChatGPT 4 produce a synthesizable and functional Verilog description for a programmable Spiking Neuron Array ASIC, by providing ChatGPT 4 natural language prompts. The AI-generated design was verified in simulation using handcrafted testbenches and has been submitted for fabrication in Skywater 130-nanometer process through Tiny Tapeout 5 using an open-source EDA flow. The idea here is closing the loop: using AI to design AI chips.

A B2B sales platform for automotive software

General Motors, global automotive supplier Magna, and technology company Wipro have teamed up to develop a B2B sales platform for buying and selling embedded automotive software. The platform, called SDVerse, aims to revolutionize the automotive software sourcing and procurement process. In addition to the founding members, a “launch partner” group is already in place including Ampere (the EV and software branch of Renault Group), FEV, Forvia, HL Mando, NXP Semiconductors, TTTech Auto, and Valeo.

Further reading

A new white paper from IPC, titled “Outlook for Data Analytics in the Electronics Manufacturing Industry”, addresses the theme of data analytics applications for use cases such as advanced prevention of downtime, automatic process drift correction using feedback between machines, data-driven feedback to design, simulation and planning, and more.

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