CHIPS Act updates; Japan advancements; record Nvidia results; high-NA EUV ecosystem

Research papers make up a large part of this week’s news roundup, some of them from the recently held ISSCC or from SPIE 2024 Advanced Lithography + Patterning Conference. But first, some updates on US and Japan’s efforts to revive their respective semiconductor industries, and some financial results.

US CHIPS Act funding applications far exceed available resources

U.S. Secretary of Commerce Gina Raimondo has recently provided some updates on the implementation of the CHIPS and Science Act. In total, applicant companies have requested more than $70 billion in federal subsidies, roughly twice the amount of funding that is available, she said. Therefore, in her conversations with chips company CEOs asking for a certain amount of funding, Raimondo tells them “You will be lucky to get half of that.” Raimondo also said the department is prioritizing projects that will be operational by 2030. U.S. Secretary of Commerce reiterated the CHIPS Act’s goal: “We think our investments in leading-edge logic chips, leading-edge logic chip manufacturing, will put this country on track to produce roughly 20% of the world’s leading-edge logic chips by the end of the decade,” she said. “Today we are at zero.”

Japan updates: TSMC, Tenstorrent

TSMC has recently held an opening ceremony for its majority-owned subsidiary Japan Advanced Semiconductor Manufacturing (JASM) in Kumamoto Prefecture, Japan. Market research firm TrendForce forecasts the plant’s total capacity to hit 40–50K wafers per month, focusing mainly on 22/28-nanometer processes with a dash of 12/16-nanometer, paving the way for the next phase of the Kumamoto expansion. The Japanese government has reportedly said it will give TSMC up to $4.86 billion more in subsidies to help it build a second chip fabrication plant in the country.

US-headquartered AI chip developer Tenstorrent has announced a partnership deal with Japan’s Leading-edge Semiconductor Technology Center (LSTC), which selected Tenstorrent’s Risc-V and chiplet IP for its edge 2-nanometer AI accelerator. In addition to the IP licensing portion of this deal, Tenstorrent will work with LSTC to co-design the chip. Under this project, Tenstorrent will also work with Japan-based Rapidus, which is planning to offer – besides chip fabrication – also advanced packaging technologies.

Market research firm TrendForce is optimistic about Japan’s chances to regain a leading position in the semiconductor industry, thanks to its equipment/material suppliers (TEL, JSR, Screen, Sumco, Shin-Etsu), availability of talent and water, a growing presence of TSMC which includes a 3D IC research center and plans for further plants.

Financial results: Nvidia, Ansys

Nvidia has recently reported its impressive financial results for fiscal 2024. Revenue was up 126% to $60.9 billion. GAAP earnings per diluted share was $11.93, up 586% from a year ago. Non-GAAP earnings per diluted share was $12.96, up 288% from a year ago.

As for the EDA industry, Ansys has recently reported its financial results for fiscal year 2023. GAAP and non-GAAP revenue were $2,269.9 million, up 10% from 2022; GAAP operating profit margin was 27.6% and non-GAAP operating profit margin was 42.6%. Below is a breakdown of Ansys’ income in terms of Annual Contract Value (ACV). Over the life of the contract, ACV equals the total value realized from a customer.

Source: Ansys

Doubling processing speed by taking full advantage of heterogeneous platforms

Researchers from University of California, Riverside, have investigated the benefits of Simultaneous and Heterogenous Multithreading (SHMT). While most modern computing platforms are heterogeneous, in that they integrate multiple types of processing units and hardware accelerators, the entrenched programming models focus on using only the most efficient processing units for each code region, underutilizing the overall processing power. The SHMT programming and execution model, in contrast, can utilize heterogeneous types of processing units concurrently for the same code region. The team implemented and evaluated SHMT on an embedded system platform with a GPU and an Edge TPU. SHMT achieved up to 1.95× speedup and 51.0% energy reduction compared to GPU baseline.

Source: ACM Digital Library

The High-NA EUV patterning ecosystem is ready

With more than twenty-five papers presented at the 2024 Advanced Lithography + Patterning Conference, Belgian technology hub imec shared the progress made for enabling high-numerical aperture (High-NA) extreme ultraviolet (EUV) lithography. Key achievements are reported on resist and underlayer development, mask enhancement, optical proximity correction (OPC) development, at-resolution field stitching, reduction of stochastic failures, and improved metrology and inspection. With these results, imec demonstrates readiness for transferring the EUV processes into the joint imec-ASML High-NA EUV Lab, built around the first prototype High-NA EUV scanner.

Field stitching is needed because of the anamorphic lens (i.e. a lens with different de-magnification in the x and y directions), resulting in field sizes of half of the conventional scanner. At-resolution stitching will reduce the need for design changes to cope with the field size reduction. Imec also presented the advancements of metal-oxide resists (MORs) in terms of EUV dose-to-yield reduction. The selection of the specific underlayer, optimization of the development process, choice of mask absorber, mask bias and mask tonality led to a more than 20% dose reduction for lines and spaces, without increased roughness or stochastic failures. According to imec, the dose reduction work is highly appreciated by chip makers, since it leads to EUV cost reduction due to the higher scanner throughput.

Keyword spotting for devices running on energy harvesters

At ISSCC 2024 in San Francisco, French technology hub CEA-Leti presented a keyword-spotting system for always-on, voice-activated edge-AI systems suitable for devices running on energy harvesters. The chip operates down to 0.4 volts, while achieving 91 percent accuracy on ten words with a power consumption below 1 microwatt. The new architecture uses injection-locked, oscillator-based time-domain audio feature extraction (TD-FEx), where information is not coded as a voltage but as a time delay of two clock signals. According to CEA-Leti, with a silicon area of 0.15 square millimeter the new chip is at least 3.5 times smaller than prior art on the same 65-nanometer process node, and with a power of 988nW it is nine times more power-and-area efficient than ring-oscillator-based TD-FEx.

Powerful 3D-printed solenoids

A team of MIT researchers has created fully 3D-printed, three-dimensional, soft magnetic-cored solenoids that generate three times the largest magnetic fields previously reported from 3D-printed solenoids. The devices are fabricated on a customized, multi-material 3D printer that can extrude both filaments and pellets. Via manufacturing optimization, the reported solenoids are 33% smaller and can withstand about twice the current. The 3D-printed devices can be readily used to implement fully 3D-printed induction sensors. According to the researchers, the results of this work extend the state of the art in 3D-printed electronics, enabling the creation of more complex and capable solenoids for in-situ manufactured and in-space manufactured electromagnetic systems.

Credit: MIT researchers

Further reading…

… is actually further watching this week, with AI-generated text-to-video samples from OpenAI’s Sora and from Google’s Lumiere.

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