Arm’s chiplet initiatives; SoftBank reportedly planning a chip venture; new Siemens Veloce systems; new ADC architecture

What’s cooking at Arm after the recent, emboldening surge in its market capitalization? On the one hand, the company has unveiled two initiatives aimed at taking center stage in the emerging chiplet-based market and ecosystem. On the other hand, Masayoshi Son – CEO of SoftBank Group, the Japanese holding company that owns a 90% stake in Arm – is reportedly looking to raise up to $100 billion for a chip venture that will rival Nvidia, with a potential help from Middle Eastern investors. Should this be confirmed, some questions would arise. Why would SoftBank challenge Nvidia? After all, the surge in Arm’s market capitalization seems to be an effect of the role played by Arm CPUs in Nvidia-based AI solutions. Does SoftBank feel that the pervasiveness of Arm CPUs is an advantage position enabling it to pursue additional AI opportunities, besides Nvidia? Will Arm continue to be a pure-play, neutral IP provider, if SoftBank gets involved in a “chip venture”? As for the Middle Eastern potential investors, the report does not mention any country names, but if it were Saudi Arabia or the UAE then SoftBank would be knocking on the same doors as OpenAI’s Sam Altman – who is also reportedly hoping to raise money from investors in that geography, for his gigantic semiconductor plan. Should those investors actually agree on satisfying all these requests, the role of Middle East in semiconductor funding would become an additional geopolitical factor to consider in the context of the current “chip war”. And now, let’s move to the news.

SoftBank reportedly planning a “chip venture”

SoftBank Group’s CEO Masayoshi Son is reportedly looking to raise up to $100 billion for a chip venture that will rival Nvidia. According to the report, the project – code named Izanagi – will supply semiconductors essential for artificial intelligence. SoftBank would inject $30 billion in the project, with an additional $70 billion potentially coming from Middle Eastern institutions.

Arm unveils its chiplet strategy

Arm has recently unveiled two initiatives that demonstrate the company’s intention of playing a pivotal role in the emerging chiplet-based market and ecosystem. The Arm Chiplet System Architecture (CSA), being developed with a group of more than twenty partners, will define optimal partitioning choices for chiplet-based systems to enable greater reuse of components (physical design IP, soft IP etc.) among multiple suppliers. The other Arm initiative is a newly released extension of the AMBA protocol, called CHI C2C, which aims at becoming the standard protocol for chiplet-to-chiplet communication. As explained in the architecture specification document (available from here), CHI C2C focuses on the packetization of CHI messages, making them suitable to be transported over a chip-to-chip link. The packetization format is optimized for link utilization and latency, while avoiding complex packing and unpacking schemes. The two primary use cases are Multi-chip Symmetric Multi-Processor (SMP) and Multi-chip coherent accelerator attach. According to Arm, CHI C2C is completely complementary to UCIe, as it can be transported over UCIe – which would represent the PHY layer – through its streaming interface. Companies supporting CHI C2C include Arteris, Cadence, Fujitsu, Intel Foundry Services, Nvidia, Rambus, Sanechips, Siemens EDA, SiPearl and Synopsys. In particular, Arm pointed out that Arm and Nvidia worked closely together to define and lay the foundation for CHI C2C, so Arm-based SoCs can “coherently and securely” connect to accelerators.

Siemens’ new emulation and prototyping platform

Siemens Digital Industries Software has launched the Veloce CS hardware-assisted verification and validation system. In what the company claims to be “a first for the EDA industry,” Veloce CS incorporates hardware emulation, enterprise prototyping and software prototyping. The solution is built on two ICs: Siemens’ new, purpose-built Crystal accelerator chip for emulation, and the AMD Versal Premium VP1902 FPGA adaptive SoC for enterprise and software prototyping. The new product family encompasses three offerings: Veloce Strato CS hardware for emulation, Veloce Primo CS hardware for enterprise prototyping, and Veloce proFPGA CS hardware for software prototyping. The system supports design sizes from 40 million gates up to more than 40+ billion gates, using a fully unified software architecture. The entire Veloce CS system is available in a modular blade configuration that is compliant with modern datacenter requirements.

A complete open-source EDA toolchain

Rapid Silicon has released its Raptor Design Suite, a complete open-source EDA toolchain. Key features of the suite include a FOEDAG-based open-source GUI that integrates all FPGA development tools into a single interface; the amalgamation of the generative AI-enabled RapidGPT platform; compatibility with third-party applications, including Visual Studio Code; enhancements for Yosys (synthesis) and VPR (place & route); integration with proprietary utilities for bitstream generation, JTAG programming, debugging, and an On-chip Logic Analyzer; LiteX framework support with over 50 soft IPs for IP integration.

An open N2 process design kit for designers’ training

At ISSCC 2024, Belgian technology hub imec launched its open process design kit (PDK) with a concomitant training program offered through the European “Europractice” consortium. The PDK will enable virtual digital designs in imec’s N2 technology, including backside power delivery network. The PDK will be embedded in EDA tool suites, such as from Cadence and Synopsys, providing broad access to advanced nodes for design pathfinding, system research and training. The initiative aims at overcoming the problem of restricted access to foundries’ PDKs, which has created a high threshold for academia and industry to access advanced technology nodes during their development.

New ADC architecture offers small area and low power for optical transceivers

Another innovation introduced by imec at ISSCC 2024 is a new architecture for analog-to-digital converters targeted at the optical transceivers used in optical networks within datacenters. Overcoming the limitation of conventional time-interleaved SAR ADCs, the new architecture employs a massively time-interleaved slope-ADC design. It has been used by imec to build a prototype chip working at a speed of 42 gigasamples per second. Containing an array of 768 slope-ADCs and implemented in 16-nanometer FinFET technology, the prototype chip has a core active area of just 0.07 square millimeters – at least a factor of two smaller than conventional approaches – and a state-of-the-art power consumption of 96 milliwatts. The team is already working on 5-nanometer and 2-nanometer chips, targeting sampling rates in excess of 150GS/s and 250GS/s respectively.

Foundry updates: Samsung, GlobalFoundries

In its recent earnings presentation for the 4Q 2023 financial results, Samsung Foundry stated that its development plan for GAA-based processes at the 3- and 2-nanometer nodes is tracking well, and that the orders received for 2023 reached a highest ever annual total. The company also disclosed that it has recently received a 2 nanometer-class order for an AI accelerator project, which includes HBM and advanced packaging.

Samsung has also announced that it will deliver the next generation Arm Cortex-X CPU optimized on Samsung Foundry’s latest Gate-All-Around process technology. As stated in a press release, “the companies have bold plans to reinvent 2-nanometer GAA for next-generation data center and infrastructure custom silicon, as well as a groundbreaking AI chiplet solution that will revolutionize the future generative artificial intelligence mobile computing market.”

The U.S. Department of Commerce has announced $1.5 billion in planned direct funding for GlobalFoundries as part of the U.S. CHIPS and Science Act. The funding will support three GF projects: expansion of GF’s existing Malta, NY fab; construction of a new state-of-art fab on the Malta campus; a modernization of GF’s facility in Essex Junction, Vermont, which will include the addition of GaN capabilities.

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