EDA News Roundup

Catching up on some of the news from the last thirty days or so, this week we will focus on some of the latest EDA announcements.

Ansys’ 2023 R2 release, AnsysGPT, Ansys-Altium connection

Recent announcements from Ansys include the introduction of its latest release, 2023 R2, and the limited beta release of AnsysGPT, a multilingual, conversational, AI virtual assistant for customer support. Developed using ChatGPT technology available via the Microsoft Azure OpenAI Service, AnsysGPT uses Ansys public data to answer technical questions concerning Ansys products, relevant physics, and engineering topics. Another recent announcement from the company concerns the digital connection of Altium’s electronic computer-aided design tools and Ansys simulation tools included in Ansys Electronics Desktop.

Cadence’s Joules RTL Design Studio

Cadence has announced its Joules RTL Design Studio, a new solution to accelerate the RTL design and implementation process. Front-end designers can access digital design analysis and debugging capabilities from a single, unified cockpit, which – according to the company – will enable fully optimized RTL design prior to implementation handoff. Users will also be able to leverage generative AI for RTL design exploration and big data analytics. According to Cadence, by enabling quick and accurate physical estimates, Joules RTL Design Studio can unlock up to 5X productivity and up to 25% quality of results (QoR) improvements in the RTL.

Siemens’ Calibre DesignEnhancer

Siemens Digital Industries Software’ Calibre DesignEnhancer software is a solution that – according to the company – enables IC, place-and-route and full-custom design teams to improve productivity, boost design quality and reduce time to market by automatically implementing ‘Calibre correct-by-construction’ design layout modifications much earlier in the IC design and verification process. The Calibre DesignEnhancer tool currently provides three use models: via modification automatically analyzes layouts and inserts up to 1 million+ Calibre-clean correct-by-construction vias to reduce the impact of via resistance on EM/IR and reliability; power/ground enhancement automatically analyzes layouts and inserts Calibre nmDRC-clean vias and interconnects in open tracks to create parallel runs that can lower resistance on power/ground structures and reduce IR and EM issues associated with the power grid; filler cell insertion optimizes the insertion of decoupling capacitor and filler cells required for physical verification readiness.

Siemens’ Solido Design Environment

Another recent announcement from Siemens Digital Industries Software concerns the introduction of Solido Design Environment software, an artificial intelligence-powered, cloud-ready IC design and verification solution. According to Siemens, the solution uses AI to help users identify optimization paths to improve circuit power, performance, and area, as well as to perform statistical yield analysis at a fraction of runtime compared to brute-force methods. It also features new Additive Learning technology that assists in boosting performance for design and verification teams. Siemens claims that Solido Design Environment software can help to achieve verification accuracy up to 6 sigma and higher yield at speeds orders of magnitude faster than brute-force Monte Carlo, while helping to significantly improve coverage and accuracy. In a separate announcement, Siemens Digital Industries Software has revealed that it will expand its Strategic Collaboration Agreement with Amazon Web Services (AWS). Part of the expanded collaboration concerns the development of Cloud Flight Plans, which are best-known methods and technologies for running Siemens’ EDA tools in customers’ AWS environments.

Qorvo’s Qspice

Qorvo has announced the release of Qspice, which is describes as a new generation of circuit simulation software for power and analog designers. Qspice is available free of charge, as it also enables users to evaluate and design with Qorvo silicon carbide and power solutions. Claimed enhancements over legacy analog modeling tools include support for advanced analog and digital system simulations; an upgraded simulation engine that uses advanced numerical methods and is optimized for modern computing hardware, including a GPU-rendered user interface and SSD-aware memory management; reduced overall runtimes and a 100% completion rate. Qspice also allows designers to simulate complex digital circuits and algorithms, often employed in advanced power applications.

RS new circuit simulator tool

RS has launched a new circuit simulator tool for use by the 1.3 million members of the DesignSpark engineering community. Developed in partnership with Siemens Digital Industries Software’s PartQuest Explore team, the browser-based tool provides a comprehensive environment for designing, modeling, simulating, and analyzing electronic and mechatronic circuits and systems. Specific features include the ability to sketch electronic schematics on the go, create interactive reference designs for testing and understanding applications, simulate circuits online, and more.

JuliaHub’s CedarWaves

JuliaHub has recently introduced CedarWaves, described as “a state-of-the-art solution engineered to redefine analog circuit simulation, verification, and waveform analysis.” Benefits claimed include deep insights with internal signal verification, robust waveform measurements, early error detection, efficient debugging.

Keysight’s PathWave Design 2024

PathWave Design 2024, the latest release of Keysights’ suite of EDA software tools, includes a number of innovations. Among them, a new Python API, the integration of the former Cliosoft products, and cloud support for electrothermal (ETH) simulation for radio frequency power amplifier design.

Xpeedic EDA 2023 Suite

Xpeedic has launched its high-speed digital signal integrity and power integrity (SI/PI) suite for advanced packaging and high-speed design domains. The Xpeedic EDA 2023 Suite includes 2.5D and 3D signal integrity and power integrity simulation for advanced packaging, along with three platforms to support 3D electromagnetic simulation, multi-domain co-simulation and high-speed system simulation.

EDA tools certified for the Intel 16 process

Intel Foundry Services (IFS) has recently certified a wide range of tools from the four major EDA vendors for its Intel 16 process. Certifications have been granted to Ansys RedHawk-SC and Ansys Totem; to Cadence digital and custom/analog flow; to Siemens’ Calibre nmPlatform tool for integrated circuit design verification; and to Synopsys’ digital and custom design flows. In addition to that, Cadence Design IP has been ported and silicon-tested for Intel 16 technology, and Synopsys Foundation IP and Interface IP have been optimized for the same IFS technology.

Acquisitions

Cadence will acquire the Rambus SerDes and memory interface PHY IP business. Rambus will retain its digital IP business, including memory and interface controllers and security IP.  Rambus PHY engineering teams in the United States, India and Canada will join Cadence.

This entry was posted on Friday, August 4th, 2023 at 12:18 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.