Catching up on some of the news from the past few weeks, let’s start by noting that yet another hyperscaler is developing its own AI chip: according to press reports, Microsoft is working on a device code-named Athena, currently being tested. Microsoft is reportedly accelerating the rollout following the success of ChatGPT.

Cadence leverages AI and the cloud to speed up PCB design

The new Cadence Allegro X AI technology promises to reduce the time for PCB placement and routing tasks from days to minutes, and with equivalent or higher quality compared with manually designed boards. Reduction in design turnaround time is achieved by automating placement, metal pouring and critical net routing – leveraging a scalable architecture that uses compute infrastructure on the cloud. Placement automation using generative AI enables feasibility analysis in the early phases of design. Exploring a much larger solution space than what is possible through manual methods, the technology drives optimization of metrics such as shorter wire lengths while adhering to the design constraints. Integration with signal integrity and power integrity analysis through the Allegro X Platform enables the user to optimize the designs for electrical and thermal performance. According to Cadence, the solution achieves a 10X or more reduction in PCB design turnaround time.

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Will the market dominance of EDA’s “big three” remain immune from the new factors that are impacting the semiconductor ecosystem? We tried to answer this question with the help of Laurie Balch (Pedestal Research), Harry Foster (Siemens EDA), David Kanter (MLCommons), KT Moore (Cadence), Wally Rhines (Cornami)

In Part One of this special report we focused on the factors of stability that have contributed to the creation of the EDA oligopoly (Cadence, Siemens EDA and Synopsys, of course) and still underpin the incumbents’ market dominance: a certain degree of complementarity among the ‘big three’ product offerings, and the high cost incurred by customers if they want to switch from one EDA vendor to another. We also examined the overall performance of EDA solutions for IC/ASIC design through the findings of the 2022 Wilson Research Group Functional Verification Study, which shows – on average – a 24 percent rate of first silicon success and a 33 percent rate of project completion without schedule slips. Additionally, we discussed the attitude of the EDA industry towards benchmarking and open-source tools. In this second part of our report we will address some of the criticisms that have been raised against the EDA oligopoly and will consider some potential factors of change. We will do that, again, through interviews with EDA professionals (Harry Foster, Chief Scientist Verification at Siemens EDA; KT Moore, VP of corporate marketing at Cadence; Wally Rhines, CEO at Cornami and formerly CEO at Mentor Graphics for twenty-four years), an EDA market analyst (Laurie Balch, Research Director at Pedestal Research) and an executive from a benchmarking consortium (David Kanter, Executive Director at MLCommons).

A different view on the EDA status quo: DARPA and the OpenRoad project

Is the vendor oligopoly a positive or a negative thing for the EDA users? Over the past few years, DARPA (Defense Advanced Research Projects Agency) has often expressed opinions that are relevant for a discussion on this topic. In particular, the EDA theme has been addressed by Serge Leef when he was Program Manager of the DARPA’s Microsystems Technology Office. Other relevant concepts can be found in the OpenRoad project lead by Professor Andrew Kahng from UC San Diego, one of the open-source EDA initiatives supported by DARPA. Unfortunately, neither Serge Leef – who left DARPA last year – nor any other DARPA spokesperson, nor Professor Kahng could be reached for comments, so here we will refer to documents that are publicly available online.

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Will the market dominance of EDA’s “big three” remain immune from the new factors that are impacting the semiconductor ecosystem? We tried to answer this question with the help of Laurie Balch (Pedestal Research), Harry Foster (Siemens EDA), David Kanter (MLCommons), KT Moore (Cadence), Wally Rhines (Cornami)

The global EDA market is notoriously dominated by just three U.S.-based major vendors: Cadence, Siemens EDA and Synopsys, of course. This status quo has been stable for decades; will it continue to be this stable in the future? Several new events and trends have recently started impacting the semiconductor ecosystem: US-China tensions, the AI boom, the growth of hyperscalers, massive subsidies supporting the construction of new fabs around the world etc. Will any of these new events have an impact on the EDA oligopoly? We tried to answer this question by interviewing EDA professionals (Harry Foster, Chief Scientist Verification at Siemens EDA; KT Moore, VP of corporate marketing at Cadence; Wally Rhines, CEO at Cornami and formerly CEO at Mentor Graphics for twenty-four years), an EDA market analyst (Laurie Balch, Research Director at Pedestal Research) and an executive from a benchmarking consortium (David Kanter, Executive Director at MLCommons, whose contribution will be featured in the next part of this report). In this first part, we will delve deeper into the factors of stability that have contributed to the creation of the oligopoly and still underpin the incumbents’ market dominance. Adding to the description of the status quo, we will also focus on the overall performance of EDA solutions, as well as on the attitude of the EDA industry towards benchmarking and open-source tools. The second part of our report will address some of the criticisms that have been raised against the EDA oligopoly and will consider some potential factors of change.

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