The international race for semiconductor supremacy and the impact of electric vehicles on the SiC market are among the themes of this week’s news roundup. But first, some IP and EDA updates.
IP and EDA updates: Signature IP, Defacto, Cadence
New startup Signature IP aims to innovate the Networks-on-Chip IP scenario. As the company stated in a press release, the company’s purpose is to make it easy to design and configure the NoC backbone within a chip and benefit from the flexibility of exploring the design space before committing to an architecture. “There are few commercial NoC providers to choose from, and they are typically very restrictive in their architectures and commercial terms,” said CEO Purna Mohanty. “Our flexible iNoCulator NoC configuration tool enables customers to experiment with their SoC architecture and simulate it in real time so they can optimize it at the top level.” Offered as Software-as-a-Service, iNoCulator NoC Configurator can generate both coherent and non-coherent NoCs. It enables users to change the NoC topology, experiment with different configuration settings, and simulate the results to measure throughput and latency.
Defacto has announced SoC Compiler 10.0, the new major release of its front-end design solution for large SoCs. Among new pre-synthesis design features, the ability to use both Accelera’s IP-XACT and RTL as input formats for internal and external IPs at different design steps; “ifdef” support to generate generic and configurable RTL code; a higher degree of automation in the management of design collaterals such as UPF and SDC jointly with RTL and IP-XACT; and Python native support.
