Catching up on some of the news from the last three weeks or so, let’s start with a Silicon Valley update: Tesla global engineering headquarters are moving to Palo Alto. The company is reportedly taking over the lease for the office space previously occupied by Hewlett-Packard. More news this week concern new fabs around the world and the U.S. CHIPS Act. But first, some IP and VIP updates.
IP, VIP and validation updates: Arteris, Avery, Cadence, Imperas
Arteris has launched its FlexNoC 5 physically aware network-on-chip IP, which enables SoC designers to incorporate physical constraint management across power, performance and area (PPA). According to the company, this technology enables up to 5X faster physical convergence over manual refinements with fewer iterations from the layout team. The resulting physically optimized NoC IP instance is ready for output to physical synthesis and place and route for implementation. Arteris has also formed a partnership with Risc-V IP vendor SiFive, to help speed up edge AI product development. As a result of this collaboration, SiFive has developed the 22G1 X280 Customer Reference Platform, incorporating a SiFive X280 processor IP and an Arteris Ncore cache coherent interconnect IP.
Avery Design Systems has announced a new validation suite supporting the Compute Express Link (CXL) open industry-standard interconnect. It enables system interoperability, validation and performance benchmarking of systems targeting the full range of versions of the CXL standard. According to the company, sharing the same validation suite across pre- and post-silicon enables hardware and software development teams to start system integration and validation extremely early in the project while still working with Verilog RTL simulation and emulation.
