Benefits of AI-based EDA; static linting for FPGAs; ESD diode Spice model; open-source eFPGA dev suite; PCB SI/PI analysis

A couple of ‘geopolitical’ updates. General Motors and GlobalFoundries have announced a strategic, long-term agreement establishing a dedicated capacity corridor exclusively for GM’s chip supply. Through this first-of-its-kind agreement, GlobalFoundries will manufacture for GM’s key chip suppliers at GF’s advanced semiconductor facility in upstate New York, bringing a critical process to the U.S. Thomas Caulfield, president and CEO of GlobalFoundries, said that GF will expand its production capabilities exclusively for GM’s supply chain. And the U.S. government is reportedly poised to extend restrictions to American investments that are used to finance the development of advanced technologies in China. According to the report, the executive order would most likely prohibit outright investments in some sensitive areas, like quantum computing, advanced semiconductors and certain artificial intelligence capabilities with military or surveillance applications.

STMicroelectronics and SK Hynix unveil results achieved using Synopsys DSO.ai

Synopsys’ AI-based DSO.ai design system has reached the mark of 100 commercial tape-outs. The announcement includes quotes from two important Synopsys customers, unveiling the results they obtained. STMicroelectronics, which used Synopsys DSO.ai on Microsoft Azure cloud, increased PPA exploration productivity by more than 3x, allowing fast implementation of a new Arm core, while exceeding power, performance and area goals. SK hynix cited a recent project where DSO.ai delivered a 15% cell area reduction and a 5% die shrink.

Aldec’s linting tool supports Microchip FPGA designs

Aldec has updated its Alint-Pro linting tool to enhance the support of Microchip Technology’s Libero SoC Design Suite. The new release supports automatic conversion of Libero FPGA and SoC FPGA projects into Alint-Pro’s environment for static linting and clock domain crossing analysis of hardware designs in VHDL, Verilog or SystemVerilog. According to Aldec, static linting helps detect a wide variety of design issues, including poor coding styles, improper clock and reset management, simulation vs. synthesis mismatches, incorrectly implemented finite state machines, and other typical source code issues throughout the design flow. The company maintains that CDC analysis is critical to designs with multiple asynchronous clocks and helps mitigate non-deterministic issues such as data incoherence as a result of metastability that inevitably appear in today’s large FPGA and SoC FPGA designs.

An accurate Spice model for diodes under ESD events

Si2, the Silicon Integration Initiative, has released a new electrostatic discharge compact modeling standard for diodes called ASM-ESD that aims to improve the reliability of integrated circuits. As explained in a press release, accurate Spice simulation of electrostatic discharge scenarios and circuit protection is crucial to avoid ESD failures in integrated circuits and products, but conventional diode models do not account for ESD event regimes, during which the device operates under significantly different voltage, current, and thermal conditions. The Advanced Spice Model for ESD Diodes fills this gap by capturing diode behavior under ESD event conditions.

New release of QuickLogic eFPGA development tool suite

QuickLogic has released a new version of its Aurora eFPGA development tool suite. The Aurora 2.1 release is based on open-source synthesis (Yosys), Versatile Place and Route (VPR), and bitstream generation (OpenFPGA) software. It supports all major HDLs including Verilog, System Verilog, and VHDL. The suite of tools enables FPGA designers to go from RTL-to-bitstream for QuickLogic’s eFPGA IP. As the company points out, the Aurora eFPGA user tools also support an architecture analysis mode, enabling users to tune the architecture for their application instead of being forced into a ridged fixed-size tile approach.

Xpeedic’s new package/board SI/PI/thermal analysis platform

Xpeedic has released Notus, an EDA platform for package/board signal integrity, power integrity and thermal analysis. Powered by Xpeedic’s electromagnetic and multiphysics solver engine, Notus provides a comprehensive simulation flow, including DC IR-drop and AC impedance analysis, decoupling capacitor optimization, signal topology extraction, signal interconnect modeling, and thermal analysis. Xpeedic has also announced upgrades to other solutions, such as its Metis EM simulation tool for 2.5D/3DIC advanced packaging designs, its Hermes 3D EM simulation tool, and its ChannelExpert circuit simulation platform for analyzing high-speed channels.

TSMC University FinFET Program

TSMC has launched its “TSMC University FinFET Program”, aimed at universities around the world. The program will provide educational access to the process design kit of TSMC’s FinFET technology at 16-nanometer; it will also provide access for researchers to both 16-nanometer (N16) and 7-nanometer (N7) silicon through multi-project wafer services. The imitative will be carried out through service partners in Asia, Europe and North America.

Acquisitions

UK-based Linaro, which provides software development tools and services for the Arm ecosystem, has signed a definitive agreement with Arm to acquire the Arm Forge high performance computing tools business. Arm Forge provides debug and performance analysis tools across multiple compute architectures for server and HPC applications. Upon completion of the acquisition, the suite of software tools will become known as Linaro Forge.

Upcoming events

Some of the highlights of the International Symposium on Physical Design, an online event scheduled for March 26-29, include a keynote from Alberto Sangiovanni-Vincentelli on “Automated Design of Chiplets”, a keynote from Burn J. Lin on “Immersion and EUV Lithography: Two Pillars to Sustain Single-Digit Nanometer Nodes”, and dozens of papers from industry and academia. Best papers candidates are “FastPass: Fast Pin Access Analysis with Incremental SAT Solving”, from The Chinese University of Hong Kong; and “Placement Initialization via Sequential Subspace Optimization with Sphere Constraints”, from National Chung Hsing University and University of California San Diego. The event will include a panel on the theme “EDA for domain specific computing”.

Further reading

At the 2022 edition of IEDM, TSMC disclosed some details about its N3 and N3E processes. Interesting analysis and comments on the TSMC’s presentations can be found in this article from SemiWiki’s Scotten Jones.

Also concerning TSMC is the third part of the Taiwanese foundry history, by TechInsights.

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