Tech giants have been in the news over the past few days for a wave of workforce reductions: the list includes Alphabet (Google), Amazon, Microsoft, Meta (Facebook), and IBM. In at least two cases, these cost-cutting moves are accompanied by new investments in artificial intelligence: Alphabet reportedly plans to double down on AI, and Microsoft has just announced the third phase of its long-term partnership with OpenAI through a multiyear, multibillion dollar investment. Let’s now move to this week’s news roundup, starting with some EDA updates.

EDA industry Q3 2022 numbers

According to the latest report from the ESD Alliance, the Electronic System Design industry revenue increased 8.9% from $3,458.2 million in Q3 2021 to $3,767.4 million in Q3 2022. The four-quarter moving average, which compares the most recent four quarters to the prior four, rose 13.4%. Exceptions to these good results are the Semiconductor Intellectual Property (SIP) product category, with a 1% revenue decrease, and the Japan region with an 8.5% revenue decline. The EMEA region (Europe, Middle East, and Africa) reported just a 0.2% increase in Q3 2022.

New PCB signal integrity tools from Keysight and Avishtech

Keysight has introduced the Electrical Performance Scan (EP-Scan), a new high-speed digital simulation tool that supports rapid signal integrity analysis for hardware engineers and printed circuit board designers. According to the company, uncertainty about the length of the SI analysis phase performed by SI specialists creates a bottleneck in the PCB design cycle and delays time-to-market. EP-Scan addresses SI analysis bottlenecks by giving hardware designers diagnostic tools to correct designs earlier and meet development schedules.

Avishtech has launched two new low-cost toolsets, Gauss SI and SI Pro, to rapidly construct PCB stackups and simulate for impedance and loss. According to the company, up until now these capabilities were only available to large corporations, who could afford very expensive software, whereas Gauss SI and SI Pro enable every board designer and engineer to specify their stackup and design for impedance and signal integrity.

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Catching up on some of the latest news after seasonal holidays – but skipping the CES announcements overload – let’s start by briefly mentioning the recent Risc-V Summit where a Google executive spoke about Google’s support for the porting of Android to Risc-V: here’s the video of the speech.

Accellera to develop a Clock Domain Crossing standard

Accellera has announced the formation of the Clock Domain Crossing (CDC) Working Group, with the goal of defining a standard CDC collateral specification to ease SoC integration. Currently, lack of standard means that different CDC verification tools generate incompatible IP-level CDC collateral. This scenario is causing a CDC verification problem when the SoC teams source IP from IP providers that use a different tool for their own CDC verification.

PDF Solutions and proteanTecs to collaborate on analytics-telemetry solutions

PDF Solutions, a provider of semiconductor data analytics, and proteanTecs, a specialist of on-chip telemetry, have announced a collaboration on combined solutions intended to provide deeper insights on semiconductor yield, quality and reliability. The collaboration includes PDF Solutions’ Exensio Analytics platform, advanced AI/ML models and DEX data exchange network, and proteanTecs’ agents with cloud/edge analytics based on ML-driven chip telemetry. According to the two companies, the combined solutions will deliver unique benefits, such as adaptive test capabilities to further improve test quality and reduce DPPM (defective parts per million), enhanced device quality grading for downstream testing, and more insights around RMAs (return material authorizations) from in-field degradation monitoring.

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