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 EDACafe Editorial
Roberto Frazzoli
Roberto Frazzoli
Roberto Frazzoli is a contributing editor to EDACafe. His interests as a technology journalist focus on the semiconductor ecosystem in all its aspects. Roberto started covering electronics in 1987. His weekly contribution to EDACafe started in early 2019.

TSMC in Arizona; IEDM papers; new radar architecture

 
December 9th, 2022 by Roberto Frazzoli

As the industry celebrates the 75th anniversary of the invention of the transistor, geopolitical issues keep making news with Taiwan-headquartered TSMC stepping up its commitment to U.S. fabs. Several updates this week concern technological advancements presented at the IEDM conference.

TSMC to increase its Arizona investment

TSMC has announced that in addition to its Arizona’s first fab, which is scheduled to begin production of N4 process technology in 2024, it has also started the construction of a second fab which is scheduled to begin production of 3-nanometer process technology in 2026. The overall investment for these two fabs will be approximately US$40 billion, representing the largest foreign direct investment in Arizona history and one of the largest foreign direct investments in the history of the United States. TSMC Arizona’s two fabs are expected to directly hire 4,500 employees and, when complete, to manufacture over 600,000 wafers per year. This investment has reportedly sparked concerns in Taiwan, prompting the local government to reassure on TSMC’s commitment to the island. However, according to another report TSMC is planning to move all its 3-nanometer production to the U.S., which would enable Apple to equip its future iPhone 15 models with a new 3-nanometer processor made in the United States.

More news updates related to geopolitical issues concern two European tech leaders: Belgian research center Imec has signed a Memorandum of Cooperation on advanced semiconductor technologies with newly created Japanese company Rapidus; and ASML’s EUV litho equipment will probably be subject to further export restriction as the Dutch government is reportedly planning to enforce new controls on sales of chip-making equipment to China.

Avery’s SimXAXT new release

Avery Design Systems has announced a major new release to its SimXACT analysis solutions, adding features for sequential false X analysis and automatic repair and improved analysis and debug of clock gating logic. The new release also improves overall runtime performance. SimXACT automates the tedious process of analyzing X propagations in gate-level simulations due to RTL vs. gate-level mismatches. As the company explains in a press release, these issues typically arise from gate-level simulator X-pessimism handling in glue logic and gated clocking and overly pessimistic library cell modelling.

Technological advancements from IEDM 2022

Here is a quick overview of just some of the many innovations presented at the recent IEEE International Electron Devices Meeting (IEDM).

Intel’s latest hybrid bonding research shows an additional ten times improvement in density for power and performance over the company’s last year presentation. Continued hybrid bonding scaling to a 3 micron pitch achieves similar interconnect densities and bandwidths as those found on monolithic system-on-chip connections. Intel also demonstrated a gate-all-around stacked nanosheet structure using 2D channel material just 3 atoms thick, and stacked ferroelectric capacitors that can be used to build FeRAM vertically on a logic die. More breakthroughs from the microprocessor giant include a viable path to 300 millimeter GaN-on-silicon wafers, and “transistors that don’t forget, retaining data even when the power is off.”

Belgian research center Imec presented a semi-damascene integration approach for implementing the vertical-horizontal-vertical (VHV) scaling booster – intended to enable 4-track standard cells. The semi-damascene process enables cell boundary scaling down to 8nm tip-to-tip in the middle-of-line layers, providing self-aligned edges. A booster that designers can use for packing standard cells tighter, representing a 21 percent area gain over 5T designs. Imec also presented a Monte Carlo Boltzmann modeling framework that uses microscopic heat carrier distributions to predict 3D thermal transport in advanced RF devices intended for 5G and 6G wireless communication.

French research institute CEA-Leti reported development of a gesture-recognition solution based on piezoelectric micromachined ultrasonic transducers and spike-based beamforming, with an estimated power consumption of 0.41 μJ/frame.

Ambarella’s centralized radar processing

As opposed to edge-processed radars, the new centralized radar processing architecture developed by Ambarella for automotive applications promises a 6x bandwidth reduction for radar data transport, low power consumption due to order of magnitude fewer antenna MIMO channels, and 0.5 degrees of joint azimuth and elevation angular resolution. Key to these performances is the use of AI software to dynamically adapt the radar waveforms generated with existing monolithic microwave integrated circuit (MMIC) devices, and the use of AI sparsification to create virtual antennas. Additionally, the new architecture also enables dynamic allocation of the processing resources based on weather or traffic conditions, which can’t be done with an edge-based architecture where the radar data is processed at each module, and processing capacity is specified for worst-case scenarios.

Mayfield-Silicon Catalyst alliance

Venture capital firm Mayfield and semiconductor incubator Silicon Catalyst have formed an alliance to foster startup innovation. Under the terms of the agreement, Mayfield will invest capital in and provide mentoring to the majority of seed stage companies admitted to the Silicon Catalyst Incubator/Accelerator and evaluate them for follow-on investments. Over the last five years, Menlo Park-based Mayfield has partnered with the founders of Alif Semiconductor, Frore Systems, Fungible, Graphwear, Nuvia, Recogni, and a couple of stealth startups.

Further reading

Belgian research institute Imec has published a long and detailed article on backside power delivery, with a description of the processing steps involved in the construction of buried power rails and nano-through silicon vias.

In a blog post, Nvidia has summarized the papers submitted by its researchers at the recent NeurIPS conference, with advancements on a range of AI topics such as diffusion-based generative models, training of generalist AI agents, creating 3D shapes based on 2D images, inverse rendering, and more.

In an article, microprocessor analyst Linley Gwennap maintains that the legal battle between Arm and Qualcomm – following the acquisition of startup Nuvia and its Arm-compatible CPU design – may in the end damage both companies – as Microsoft released Windows for Arm but has granted Qualcomm exclusive rights to serve this market.

IEEE Spectrum magazine has devoted a special report to the 75th anniversary of the invention of the transistor.

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