New export controls have been in the spotlight over the past few days. Other news this week include several EDA updates and some interesting academic research.
New U.S. controls on export to China
The U.S. Government is implementing new export controls on advanced computing and semiconductor manufacturing items to the People’s Republic of China. Details of the new rules can be found here and here. According to Bloomberg, these additional restrictions will not apply to the China-based fabs owned by South Korean chipmakers SK Hynix and Samsung. In fact, SK Hynix Inc has reportedly said it has received authorization from the U.S. Department of Commerce to receive chip equipment needed for its chip production facilities in China for one year, without seeking additional licensing requirements.
Cadence Certus aims to accelerate design closure
Cadence has announced the new Certus Closure Solution environment, to automate and accelerate the complete design closure cycle – from signoff optimization through routing, static timing analysis and extraction. Key to acceleration is a massively parallel and distributed architecture enabling concurrent processing. According to Cadence, the solution supports the largest chip design projects with unlimited capacity while improving productivity by up to 10X versus current methodologies and flows.
