IDC is among the first market research firms trying to provide an initial assessment of how the Ukraine war will affect ICT spending and technology markets worldwide. Consequences are expected on many aspects of the business environment – and will arguably affect the semiconductor ecosystem, too. Hoping for peace, let’s now move to some tech news.
Incubators updates: Analog Devices (Ireland), Infineon (Hong Kong)
Analog Devices will invest €100 million over the next three years in ADI Catalyst, a 100,000 square foot custom-built facility for innovation and collaboration located at its campus in the Raheen Business Park in Limerick, Ireland. This latest phase of expansion will also see the creation of 250 new jobs in the Irish market by 2025. The Catalyst project is supported by the Irish Government through IDA Ireland.
Hong Kong Science and Technology Parks Corporation (HKSTP) has partnered with Infineon Hong Kong in a three-year co-incubation program targeted at microelectronics startups.
Advanced packaging and 3D updates: Apple’s Ultrafusion, Graphcore’s Wafer-on-Wafer
Apple has recently announced M1 Ultra, its new Arm-based SoC that will power the next Mac personal computers. The device uses Apple’s UltraFusion packaging architecture to interconnect the die of two M1 Max chips through a silicon interposer conveying more than 10,000 signals, providing 2.5TB/s of low latency bandwidth. This enables M1 Ultra to behave and be recognized by software as one chip, so developers don’t need to rewrite code. The new SoC consists of 114 billion transistors and features a 20-core CPU, a 64-core GPU, and a 32-core neural engine.
Graphcore has recently unveiled what it claims is the world’s first 3D Wafer-on-Wafer processor – the Bow IPU – built using TSMC’s Wafer-on-Wafer 3D technology. In the new device, two wafers are bonded together to generate a new 3D die: one wafer for AI processing, which is architecturally compatible with the preexisting Graphcore GC200 IPU processor, and a second wafer for power delivery die. By adding deep trench capacitors in the latter die, right next to the processing cores and memory, Graphcore claims to be able to deliver power much more efficiently – enabling a 40% increase in performance. More details have been disclosed in this EETimes article. As the company explained, the two wafers are bonded – metal sides together – without any interstitial bumps, in a sort of cold weld, achieving an extremely high density of interconnect. The device also uses ‘back-side through-silicon vias’ (BTSVs) which allow connection to layers inside the wafer sandwich. Graphcore points out that Wafer-on-Wafer is different from chip-on-wafer technologies, and that aligning two entire wafers is easier rather than two die. This – along with the use of an ion etch process for BTSVs – results in a finer connection pitch.
Graphcore has also announced it will use the next generation of its IPU technology to build an AI supercomputer that will reach over 10 ExaFlops of AI floating point compute. The system – called ‘the Good Computer’ in honor of computer science pioneer Jack Good – is expected to be available by 2024.
