With its new ImperasDV solution, the company aims at enabling all RISC-V developers to accomplish the complex task of processor IP verification more efficiently
“The greatest migration in verification responsibility in the history of EDA,” from processor IP vendors to SoC designers: this, according to Imperas Software, is the challenge facing SoC development teams as they take advantage from RISC-V customization capabilities. One of the reasons for the success of RISC-V is undoubtedly the possibility for any SoC developer of adding some degree of customization to the basic instruction set architecture, while saving the processor compatibility with the RISC-V ecosystem of supporting tools and software. The other side of the coin, however, is a heavier verification burden on the SoC development team: as opposed to an off-the-shelf processor IP which is pre-tested by the vendor, a customized processor needs to be verified by whom performed its customization. Addressing this challenge, Imperas Software has recently launched ImperasDV, an integrated solution for RISC-V processor verification.
This new product is the main subject of the video interview that Larry Lapides, Vice-President at Imperas Software, has recently given to EDACafe’s Sanjay Gangal. In this article we will take a closer look at ImperasDV, adding a few details to the video interview content. We will also briefly discuss another major part of Imperas’ product offering, virtual platforms for embedded software development – along with the promotion of open model library availability through the Open Virtual Platforms (OVP) industry consortium. Based near Oxford, UK, with offices in Silicon Valley and Tokyo, Imperas software was founded in 2008 by Simon Davidmann, an EDA veteran.
