The Mirabilis Design approach to system-level architecture exploration

Achieving 5x battery life without any hardware changes: according to Deepak Shankar, Mirabilis Design’s founder, this is an example of the benefits that can be obtained through his company’s system-level architecture exploration solution, based on the VisualSim IP libraries

System-level architecture exploration is an increasingly important task for designers, especially when it comes to optimizing power or performance for complex SoC designs. Software company Mirabilis Design (Sunnyvale, CA) has chosen to address this specific area, through a system-level simulation platform – its flagship product VisualSim Architect – that employs IP libraries built in-house. In the last year and a half, the company has seen almost a 6x increase in revenue and almost a 15x jump in the number of customers (source: Mirabilis Design data), partly owing to the new remote collaboration needs brought about by the Covid-19 pandemic. Deepak Shankar, founder and Vice President of Technology at Mirabilis Design, has reiterated the key concepts of his company’s approach in the video interview he has recently given to EDACafe’s Sanjay Gangal. For this article, he has also answered a few additional questions.

 System-level optimization challenges and the benefits of architecture exploration

Shankar started out by recalling the Mirabilis approach: “We provide system-level intellectual property for architecture exploration and analysis using an extremely high performance simulation platform that allows users to very quickly study the performance, power and functionality of semiconductors, embedded systems and the software. Using our environment, companies can eliminate all surprises before they start doing the integrational development. We have [customers] ranging from very large semiconductor companies to start-ups that are involved in AI SoCs, to large defense contractors building radars and flight avionics, to automotive companies doing autonomous driving.

The main goal of all of them is to ensure that there is no bottleneck, they size their system correctly and they partition their software across all the available resources before they go to start doing development.” According to Shankar, the complexity of today’s chips calls for this approach and makes other solutions inefficient: “The thing is, the system-on-chip is really a system,” he said. “Today, if I look at the AI SoCs, autonomous chips, radar chips, avionics chips, they’re much more than just a processing unit. They have accelerators, interfaces, DMAs, so many different functionalities in there. I have got forty or fifty different interfaces, and I have got to verify that. And if I put that on a Palladium box or on an FPGA board, how do I know that I’m getting all the sensor data on these interfaces coming at the appropriate time, at the appropriate sizes? Only a system overview model can give you that kind of information.” This approach provides tangible results, Shankar maintained: “Based on the feedback from customers, we’ve seen two things that happen: one is they are being able to cut the time it takes for development because they reduce the number of repeats and number of bugs that they would find in implementation; and they are getting a highly, more optimized product.”

Multiple levels of architecture exploration

Architecture exploration is a widely used expression these days, and it’s often cited as one of the opportunities made available by High Level Synthesis. To better explain the Mirabilis approach, Shankar reminded that architecture exploration may take place at multiple levels – as it may be focused on different targets: “Systems, like an autonomous driving platform; SoCs, like an AI processor; micro-architectures, like a RISC-V core. The HLS focuses on the architecture exploration of the gates within the small set that can be synthesized at a time,” he observed. “You typically do an architecture exploration before selecting blocks to synthesize.” T

he Mirabilis approach extends to the higher levels of architecture exploration, with a set of holistic goals, as Shankar explained: “System-level architecture focuses on the total implementation of the SoC or the system which includes performance, power and functionality. The optimization happens at the software functional level, such as task partitioning into cores or neural networks, or at the hardware level of assigning hardware pieces (both custom and standard) across a topology. The topology is the interconnect, which can be AMBA AIX or Arteris NoC or custom nodes. Also, the metrics for decision at the system-level tend to be different: latency to complete a given sequence of functions, throughput at the interface and memory, buffer occupancy, hit-ratio at the cache, power consumption for a software task or device or an entire system, impact of a power management algorithm on the total SoC, efficient usage of cores and neural network, reliability of safety critical application in an event of a failure.”

Requirements for a system-level architecture exploration solution

The goals of system-level architecture exploration call for a solution that matches a set of specific requirements, according to Shankar: “You need a really fast simulation with a discrete-event engine; a large library of IP blocks so it is easy to make large changes, such as going from an Arm Cortex A53 to a SiFive RISC-V u74, or from x86 to Arm N1, or moving from a Tensilica core to a custom neural network to implement an AI algorithm. The last piece required is to have all the statistics and metrics readily available. These are the three pillars of VisualSim from Mirabilis Design. We have over 500 IP blocks. This will cover every type of SoC design. In addition, we also have a development environment for custom components, arbiters, schedulers, queue management, power management etc. For the statistics, we have both standard items like those listed above or the user can specify their own. The model automatically generates these. Lastly, we have an Insight Engine which can tell you what is wrong in the system, when the problem occurred and which other device is responsible for it.”

In addition to that, some specific requirements are placed on the models used by the simulator – if the solution is to cover multiple levels of architecture exploration, including micro-architectures. “The system-level models can be of many different types. It depends on your analysis and level of information available,” Shankar pointed out. “For example, at an early stage the models focus on timing correctness with power considered for active and passive states. When more information is available or the focus has moved to the micro-architecture, the models get refined (using a different library block) with timing, power and functionality being accurately defined similar to the RTL or board-level. The IP blocks provided by Mirabilis Design in VisualSim are available at all levels of abstraction. We have a notion of polymorphism. This means the topology can be maintained and the user can simply replace individual blocks without replacing the entire models. This allows for easy transition from one level to another.”

Ensuring model accuracy

In a model-based simulation approach, model accuracy is clearly a key issue in terms of fidelity to the real hardware. As Mirabilis builds its models in-house, measures put in place by the company to ensure model accuracy are a very relevant point. Shankar recalled the two reasons why Mirabilis has chosen to build its models in-house: “First problem is, very few vendors actually provide architecture models. As a matter of fact, even the largest supplier of IT processor cores has stopped providing vendor models for certain processors. The other reason, each one of these models would have its own interface, so as you are going to try to integrate all of them it becomes a nightmare, then we are expected to provide custom wrappers. When you have 200 vendors, it’s very hard to do that. So those are two reasons why we decided to go with building our own models.”

This decision prompted Mirabilis to put in place a rigorous model building method: “We have a very stringent verification process,” Shankar said. “We have about forty benchmark markers, and only when we’ve passed through those forty benchmarks we say: yeah, this is correct.” The company employs two different processes, one for the models for which some IP is already available, and another one when nothing is available. “When something is available, we would load the software, we would run it, we would generate all the statistics from the real chip, put it into the model and test,” Shankar explained. Then they would run the forty benchmarks, covering functionalities such as cache access, interfaces sending data to DMA, activity in the pipeline etc., or combinations of multiple functions. A different process is used to build models when no IP is available: “As a matter of fact, [sometimes] even the spec is not complete,” Shankar pointed out. “In those cases, we use the old-fashion way of putting columns and cells in Excel and verify it that way. We start with the simple scenario, slowly build up on it, and we verify that, yes, this is working correctly.” Mirabilis claims to have many success stories highlighting the accuracy of its models.

Besides accuracy, the availability of a wide range of models is also a key competitive advantage of Mirabilis, according to Shankar, when comparing VisualSim to solutions offered by other EDA vendors: “Synopsys with Platform Architect and Virtualizer come closest to what we offer,” he said. “Virtualizer is good for early software development. They have abstract models for the processor and allow other models to be constructed using SystemC. Platform Architect has some processor models and has tested with vendors providing SystemC models; users can also construct SystemC models. Platform Architect is good when you are integrating a model with existing IP. If you need to build new IP or work with models for which IP is not available it is very hard, unless you have lots of resources. Also, there is no flexibility in swapping models of different levels of abstraction. For example, IP blocks are not available for Arm Cortex beyond A57. For these the user will be out of luck. We build and verify all our models, hence we have models for blocks that vendor does not provide [in its] IP libraries. Also, we turnaround new libraries within two-three days. This is a major advantage.”

Power analysis enabled by architecture exploration – and two case studies

The single most important application of system-level architecture exploration is power analysis, as low power consumption is a key requirement for a wide variety of battery-powered end products – ranging from smartphones to electric vehicles, to IoT devices. In fact, Mirabilis is attaching great importance to power analysis: “What we’re advocating is when you’re starting to think about building a new product, do not just think of performance, area, weight, and size. Think about how it does impact the power,” Shankar said. He then provided an example of the benefits achieved by a Mirabilis customer, a manufacturer of an adventure camera: “[They] went from about thirty minutes of video recording time to two hours and twenty minutes of video recording without making any changes to the hardware, just because they were able to look at the entire system, and they were able to look at places where they could reduce the power consumption by combining multiple memory accesses, combining different tasks, doing some shifts between tasks.

That way they’re not overlapping, and that will get your power down. A lot of tweaks can be done in your design even without having to make any difference to your hardware and software.” During the video interview, Shankar provided another example concerning a Mirabilis customer that was designing a chip, initially with a core running at 1.5 gigahertz. VisualSim enabled the customer to spot huge power spikes during processing, which Mirabilis helped flattening by avoiding simultaneous tasks. “When we did that, the power just dropped,” Shankar recalled. “And they started saying, ‘Hey, wait a minute. I can try this at 1 gigahertz, I can try this at 810 [megahertz].’ So they went from about 1.5 gigahertz to about 780 [megahertz]. Price went down, thermal cost went down, the amount of power went down, their battery life went up, and they had the same performance. So that power performance trade-off must be made an integral part of your development process. It should not be an afterthought; it should be the main focus of your design.”

Reusing models for verification, software development, field testing

In the Mirabilis approach, models used for architecture exploration can have other applications, too. “Another big area where a system model can be re-used,” Shankar said, “is the verification after you’ve got your pre-silicon stage, but you have your RTL ready. The second area, which is even bigger, is really the software development. The software guys need to know what happens if I put this loop here with this control function. Does it actually trigger the jet controller? does [an IoT device] actually send this message off to the data center and get a response back? So that functionality is also enabled by a system-level model. The third one – which is really overlooked by a lot of companies, except for defense contractors – is the area around the field testing.

A lot of times, the chip is actually in a big box that is in a secure area or is in a vehicle that’s going around on the street. It’s impossible to test it in the field, but if you have a system level model, which is what the VisualSim model is, you can replay what is happening in the real car, or in the train, or in a tank, or in an aircraft. You can put that in the model and then recreate the same scenario and figure out where the problem is. So the system model can go beyond to doing chip level or RTL level verification on a board or an FPGA; it can be used for the early software validation and for field testing.” Another area where the Mirabilis solution is used is collaboration among team members scattered around the world: “We’re the only place in the design process of semiconductors where you can get a global view of your entire chip, “Shankar pointed out. According to Shankar, a system-level model provides all team members an immediate view of the impact that a change in a part of the design will cause on all the other parts, with better immediacy than RTL.

Helping the RISC-V community

One of the points discussed by Shankar was Mirabilis Design’s relationship with the RISC-V community, where architecture exploration helps assessing the impact of instruction set extensions or other developments. “We’re seeing a lot of R&D [on RISC-V] both in universities and in research centers, primarily China,” he said. “We’re seeing a huge amount of work where people are looking at, how do I do the same functionality I can get on an x86 or an Arm A77 or an N1 using my RISC-V chip? [This] means adding instructions to the ISA, changing the pipeline, providing different reconfigurable clusters of cores, adding a number of cores without increasing the clock speed.

But RISC-V is still new, so they need to verify every single aspect, and just verifying it at the RTL level or at the DSM level is insufficient, because changes in one place may have a huge impact on another one. Example, if I change the number of outstanding requests on my load-store execution unit on my processor, it might impact the right batch on my L2 DDR4 memory. And that’s where we get into play.” Mirabilis Design announced its VisualSim RISC-V system modeling and simulation environment in May 2020 with this press release.

The hybrid processor model

Shankar also described the concept of ‘hybrid processor model’ recently introduced by Mirabilis Design. “The hybrid processor is an enhancement to [our IP library] and is a big leap for those working with new processors, or a combination of processors of different sets like Tensilica, Arm and RISC-V. Earlier we had different model for the processor when used at different types of analysis. With hybrid processor, you can reuse the same block with different parameter values,” he explained. “It’s something that we’ve been thinking for a long time. And I think the industry has also been trying to do it, but they haven’t really had a success. So this is kind of our first foray into that. The challenge is there are so many different parts of the design process where system models are required. You have the conceptual, like an R&D engineer, you have the development architect, you have the marketing guys, you have the customer that’s going to try to integrate this chip into a bigger system.

Now, the commonality of all of them is they need models to be able to verify. What is common among all of them? Your interfaces are common, the sensors or the input internet or input ethernet are common, your output – which is either an egress port going out to the internet, or a display or an instrumentation panel – is common. What we’ve done with the hybrid processor is we allow you to re-use the same model across the design process. You might say, ‘Hey, that’s not a big deal, If I have this thing in C++, I could do it very easily.’ Yes and no,” Shankar observed. “The problem is every model that is being used at those different levels for the inside of the chip, tends to be completely different. Interfaces are completely different, the structures or what we call the transactions are completely different. What we’ve done with the hybrid model is we have created a stochastic model that a concept engineer can use. We have created the transaction level model that a development engineer can use, a verification guide with a cycle-accurate model, and also the same thing can be used by customers.

Now, the interesting thing is all of them have the same interface. So I just swap out one, to another one. The second side of it,” Shankar continued, “is the fact that these models have different levels of data available. For example, you might have all the details of the cache and the memory, but very little on the pipeline core. Or you might have the pipeline core, the cache and memory, but very little details of software; or you might have all of them, or none of them (…). Or you don’t have software: no problem, we have a profile-based software generator. Or you don’t have the cache addresses: no problem, we have a tool that very intelligently generates the addresses based on the profile of your software. So we have created a whole umbrella of items that allows anyone that’s building a new SoC to be able to pick this up and select from that library of IPs what exactly he would require.”

Latest product update: the AI Processor Designer

The first application of the hybrid processor model concept is the latest update in the Mirabilis product offering: VisualSim AI Processor Designer. The new solution is targeted at accelerating time-to-market of new AI technology, eliminating under-design and over-design, and providing a configuration platform for end-users.  VisualSim can be used for the design of AI processors, partition AI algorithms on a System-on-Chip, and test the performance of an AI processor in various applications. VisualSim AI contains configurable, source-code provided Intellectual Property for processor cores, custom AI designer, task partitioning utilities, cache, memory, storage, peripherals, interfaces, neural nodes and interconnect.

According to Mirabilis, the associated Insight Engine quickly detects the source of bottlenecks, performance limitations and higher power consumption in an AI SoC architecture. The platform also integrates into the FPGA verification and early software development. Features claimed by Mirabilis include enabling an architect to rapidly construct a model by configuring the IP and assembling the topology in a graphical modeling; allowing the user to run AI workloads and generate traffic on different interfaces; simulating the model to allocate tasks between cores and accelerators, partition the behavior into hardware and software, size the system parameters, trade-off response time and power consumption, select the scheduler for the neural network, and manage the queues and flow control. Users can run software on the target architecture to view the expected response times, network throughput, cache hit-ratio, and memory bandwidth.

Over 200 different demos accessible from www.mirabilisdesign.com

Lastly, Shankar suggested visitors of the company’s website – www.mirabilisdesign.com – to check the demos available. “You go to this thing called Launch Demos, and you can actually see a list of over 200 different demos. You can click on one of them and you can bring up that model and run a simulation right on your desktop. No other software is required. You can run a VisualSim model right off our website,” he concluded.

Categories: EDACafe Editorial, Video Interview

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