A closer look at Cadence’s new Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems

As gate count of advanced chips gets bigger and bigger, design teams need more powerful emulation and prototyping systems to reduce time-to-market. Cadence, for its part, is responding to this need with the introduction of its Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems, the latest generation of a coordinated solution that the company has dubbed “Dynamic Duo”. Let’s now take a closer look at these two new systems with the help of Paul Cunningham, Senior Vice President, System & Verification Group at Cadence, who recently gave a video interview on this topic to Sanjay Gangal from EDACafe.

EDACafe interviews Paul Cunningham, Senior Vice President, System & Verification Group at Cadence

Doubled capacity, 50% performance increase

The key to improved performance and capacity – compared to the previous generation of these systems, Palladium Z1 and Protium X1 – is the adoption of new processing engines. “They are powered by two different chips,” Cunningham explained. “Palladium Z2 is powered by a custom ASIC we actually built here at Cadence, (…) and Protium X2 is based on a massive capacity, leading edge Xilinx FPGA, the VU19P.” As Cunningham pointed out, Cadence has built two entirely new platforms around these chips, with new rack and new boards, achieving significant results: “Within the same rack footprint [as the previous generation], we are doubling the capacity per rack and we are increasing the performance by 50%. So there’s a very significant uplift in both these platforms.”

Unified compile across the two systems

Besides performance, a major point stressed by Cunningham is the fact that Palladium Z2 and Protium X2 make up a closely coordinated solution. “We’re maintaining what we call unified compile and unified experience between the two products,” he said. “So the whole way that you connect to test bench – connecting virtual interfaces, physical bridges, PCI, USB, Ethernet connectors – and the whole way you run a software program on a design on these platforms, it’s all completely unified between the two. This makes it very, very easy for you to move tests and simulations from Palladium to Protium, and that’s why we call [this solution] our Dynamic Duo.”

Palladium Z2, the “ultimate debug machine”

Cunningham pointed out that each of the two new systems is optimized for a different function. “Palladium Z2 is really architected right from the chip level up to the overall system to be your ultimate debug machine,” he said. “We feel Palladium Z2 compiles the absolute fastest in the industry: we can do just 250 million gates in only a few hours, and we can compile any design, 10 billion gates or more, in under ten hours. (…) We can do full at-speed debug, so you can trace any signal at any time without any impact on the performance. When your design is still in flux, every day you want to compile-run-debug, compile-run-debug; we think that the technology and the architecture in Palladium is your ultimate workhorse for that purpose.”

Cadence Dynamic Duo. Credit: Business Wire

Protium X2, the “ultimate performance machine”

Protium X2 has a different function, as Cunningham explained: “As your program progresses, if the design becomes more stable (…) the focus actually is a lot more around the pre-silicon software validation: bringing up the device drivers, the OS, running performance benchmarks on the software stack. Then you don’t need that same level of rapid iteration; you might re-build your model once a week, once every two weeks, and you’re much more focused on just the overall performance, you want to run as fast as possible pre-silicon. That’s where we feel FPGA is the right architecture, and Protium X2 is designed to be your ultimate performance machine. It’s three to five times faster than Palladium, but still with that multi-billion gate enterprise scalability.” Cunningham also provided some hardware details of Protium X2: “All four sides of the board are packed with cable connectors, there’s a lot of optical and copper interconnect to give you the best scalability. So we think it really is a very unique performance machine. (…) We’ll compile in under 24 hours for any of the designs.”

A scalable solution up to 18 billion gates

The two systems are meant to work together: “Palladium Z2 is our Land Rover,” Cunningham commented. “It’s your ultimate off-road vehicle: you can never get stuck in the mud, you can do anything, go anywhere. And Protium X2 is our Ferrari, it just shines on the racetrack. We are really delighted. Dynamic Duo 2.0 is a massive multi project, the first time – I think – that any company in our space has launched two completely new platforms simultaneously, each with new silicon chips behind them. (…) And both the systems scale by connecting multiple racks together, up to 18 billion gates at the maximum capacity of each system.”

FPGA prototyping, a key driver

Moving to the business aspect of the announcement, Cunningham recalled the results that Cadence has achieved since it started using FPGAs for its prototyping solutions three years ago. “One of the statistics we shared with our investors at the last earnings call”, he said, “is that 40% of our business last year was from Dynamic Duo customers. In only three years, we already got 40% of our worldwide business with customers buying some mix of Palladium and Protium. To me, that really shows they really appreciate to have this flexibility.” He also explained that the concept of using different compute engines optimized for different tasks was inspired by John Hennessy and David Patterson Turing lecture on domain-specific hardware/software co-design.

The value of competition

Cunningham also commented on the recent introduction of a new hardware-assisted verification solution from Siemens EDA. “I really applaud competition,” he said. “I’m first and foremost a big believer in free markets and capitalism. I really enjoy competing with Siemens EDA and with Synopsys, I think it’s good for Cadence and it’s good for our customers. Competition drives innovation and drives value creation. [Verification] is a huge thing, our customers say it is truly exponential: when they double the gate count, they square the state space. The demand and the need to accelerate verification is a hugely growing market, so we are all winning here together.” According to Cunningham, the approach adopted by Siemens EDA for its new hardware-assisted verification solution is similar to the one chosen by Cadence: “I’m delighted to see that [Siemens EDA] are now aligning with our message that you can’t deliver the best throughput in verification with one platform,”, he said, pointing out that Siemens EDA has also adopted the same Xilinx FPGA, the VU19P. “I think that’s actually the right strategy, I applaud them for going with their equivalent of a Dynamic Duo,” he added.

“Speed bridges”, a strong point in Cadence Dynamic Duo

While Cunningham declined to engage in a detailed comparison between the new Cadence systems and the competing products just announced by Siemens EDA, he did express some comments in general terms. “If I understood it correctly, [Siemens EDA] are taking their existing emulation processor and putting it together with memory on a two-and-a-half chip package. So the actual underlying emulation chip is still the same as in current Strato systems. In our case it’s an entirely new emulation chip, so (…) the entire thing is new, the actual emulation fabric itself is new.” One more point he brought up is interfaces: “We are very strong with our physical interfaces portfolio, what we call our speed bridges,” he added. “This has been a strength of Cadence for a long time: this in-circuit emulation having real adaptive cards that run at speed for all the protocols, and offering a very rich portfolio there with the same adaptive cards for both Palladium and Protium. So, I think that’s going to continue to be a very strong point in our solution.”

From Azuro to Cadence

In the video interview Cunningham also recalled that he joined Cadence in 2011 when the EDA powerhouse acquired Azuro, the startup he co-founded just after his PhD graduation in Cambridge, UK. He described his ten years at Cadence in extremely positive terms: “It’s been an amazing, amazing journey,” he said. “I’m still as inspired today as I was ten years ago when I joined.” He also enthusiastically commented his experience in the role of General Manager of the Verification Group for Cadence: “It’s a real privilege, it’s wonderful. I feel very, very lucky.” Cunningham also explained that he shares Anirudh Devgan’s vision: leveraging Cadence’s core competency in computational algorithms and computational software, and expanding on that base towards the systems space.

Cultural diversity in a “global flat team”

Transitioning from a Cambridge-based startup to a major global company was a challenge and a rewarding experience for Cunningham: “[At Azuro] we were all from Cambridge, and I had no idea how homogenous we were. (…) We were so culturally similar. When I joined Cadence, there was this massive initial challenge where you realize: wow, this is a company that is around the world, and it has all these different kinds of cultures, and people are working in different ways. They are delivering amazing software, but the way in which they are doing that can be very, very different. (…) There are lots of different ways to perform at the highest level,” he stressed. This awareness became the foundation of his managing style at Cadence: “I have a phrase I use with my team a lot: we are a global flat team, anybody anywhere in the world should feel that they have the chance to join our team, to contribute to our team and to contribute at any level. So you could have the most senior roles in my team, on my direct staff, or you can be joining straight from school as a graduate hire as your first job – you should feel that the whole world is our net,” he concluded.

More information about Cadence Palladium Z2 and Protium X2 systems can be found at this page of the company’s website, which includes video endorsements from AMD and Nvidia.

Categories: EDACafe Editorial, Video Interview

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