The 3-nanometer node is approaching, with foundries and EDA vendors preparing to address the future demanding processes. And while “downscaling” is still a key word in chipmaking, “upscaling” is becoming an increasingly important term in video consumption, designating the conversion of old low-definition video content into HDTV or even 4K. Artificial intelligence can help in this seemingly miraculous task. Completing this week’s roundup, we continue to monitor the Silicon Valley tech environment – beyond chips – with a quick look at some mobility-related startups.

TSMC’s roadmap: from N5 to N3

From August 24th to 26th, TSMC held its 2020 Technology Symposium and Open Innovation Platform (OIP) Ecosystem Forum, this year in a virtual format. On this occasion, the Taiwanese foundry provided an overview of its recent achievements and some insights on its roadmap. TSMC’s 5 nanometer N5 technology entered volume production this year, providing a 15% performance gain or a 30% power reduction, and up to 80% logic density gain over the preceding N7 technology. Building on the original N5, the company plans to ramp an enhanced N5P version in 2021, offering an additional 5% speed gain and 10% power improvement. TSMC also provided a preview of the latest member of the 5nm family – the N4 process. N4 is expected to offer further PPA improvements with reduced mask layers, while leveraging the 5nm design ecosystem. The N4 process is scheduled to start risk production in fourth quarter of 2021, with volume production in 2022. As for the next node, TSMC claimed to be “on track” with the development of its N3 process, expected to offer up to 15% performance gain, up to 30% power reduction, and a logic density gain up to 70% over N5, also thanks to “architectural innovations”. Major EDA vendors are already preparing to support N3: the achievement of TSMC certification for this future process node has recently been announced by Ansys, Cadence and Synopsys.
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Catching up on some recent news after a two-week summer break, let’s start by briefly reporting about GPT-3, the new language model from OpenAI. Other updates concern EDA, processors, and more.

 Natural language processing with 175 billion parameters

San Francisco-based OpenAI has developed GPT-3, an autoregressive language model with 175 billion parameters – ten times more than Microsoft’s Turing Natural Language Generation model. As explained in a paper, GPT-3 achieves strong performance on many NLP (natural language processing) datasets, including translation, question-answering, and cloze tasks, as well as several tasks that require on-the-fly reasoning or domain adaptation. GPT-3 can also generate samples of news articles which human evaluators can hardly distinguish from articles written by humans. As for energy usage, the researches explained that “training the GPT-3 175B consumed several thousand petaflop/s-days of compute during pre-training, compared to tens of petaflop/s-days for a 1.5B parameter GPT-2 model.” But they also added that “Though models like GPT-3 consume significant resources during training, they can be surprisingly efficient once trained: even with the full GPT-3 175B, generating 100 pages of content from a trained model can cost on the order of 0.4 kW-hr, or only a few cents in energy costs.”

TSMC 5-nanometer customers

According to a report quoted by Gizmochina, so far the 5-nanometer manufacturing capacity from TSMC has been mainly divided between eight major customers: Apple, Qualcomm, AMD, Nvidia, MediaTek, Intel, Bitmain, and Altera (this last one being listed in the report as a company by itself, separate from Intel). Gizmochina adds that Apple’s demand – “40,000 to 45,000 5nm process capacity in the first quarter of 2020” – has concerned its upcoming A14 and A14X Bionic chips and MacBook processors, while Qualcomm intends to use the 5nm process for its next flagship Snapdragon 875 processors, and MediaTek for the next generation of its Dimensity chips.
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Called MISIM (which stands for “machine inferred code similarity”), the new “machine programming system” developed by Intel in conjunction with MIT and Georgia Tech is an automated engine using neural networks to learn what a piece of software intends to do, by studying the structure of the code and analyzing syntactic differences of other code with similar behavior. As explained in a press release, Intel’s ultimate goal for machine programming is to enable software creation based on human intention expressed in any fashions, whether that’s code, natural language or something else. From an EDA perspective, it will be interesting to see if some aspects of this AI-based code analysis will prove applicable to HDL in chip design, too.

Credit: Intel

NXP microcontrollers gain Glow neural network compiler

NXP’s eIQ Machine Learning Software Development Environment now supports the Glow neural network compiler, with the goal of delivering high performance inferencing for NXP’s i.MX RT series of crossover MCUs – especially for vision and voice applications at the edge. NXP’s implementation of Glow targets Arm Cortex-M cores and the Cadence Tensilica HiFi 4 DSP, with platform-specific optimizations for the above-mentioned series of NXP products. Glow (the Graph Lowering NN compiler) was introduced by Facebook in May 2018 as an open source community project, with the goal of providing optimizations to accelerate neural network performance on a range of hardware platforms. The term “crossover” used by NXP to designate this MCU series refers to the convergence of low-power applications processors and high-performance microcontrollers. Besides Glow, the NXP’s eIQ Machine Learning Software Development Environment also includes inferencing support for TensorFlow Lite.
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