Analog verification; new Arm rumors; Intel roadmap; analog neural networks

Open-source processor IP keeps improving: SiFive has recently launched the new 20G1 release of its RISC-V Core IP portfolio, claiming up to 2.8x more performance, up to 25% lower power and up to 11% smaller area (“based on SiFive internal engineering measurement”). This is one of the many updates from the last few days, which also include EDA innovations, new Arm rumors, details on Intel’s technology roadmap, AI research advancements, and some standard news.

Mentor boosts analog verification speed

Designers of PLLs and SerDes to be implemented in advanced node geometries will be among the Mentor users who will benefit from the new Analog FastSPICE eXTreme technology, targeted at nanometer-scale verification of large, post-layout analog designs. Citing several innovations – such as new RC circuit reduction algorithms, performance improvements to the Analog FastSPICE core SPICE matrix solver, better device noise analysis capabilities – Mentor claims for the new eXTreme technology a simulation performance boost of 10X compared to its previous-generation Analog FastSPICE offering, and a 3X simulation performance acceleration compared to commercially available solutions at similar accuracy settings. According to Mentor, Analog FastSPICE eXTreme is especially valuable for analog designs containing high levels of parasitic complexity and contact resistance.

Nvidia reportedly interested in Arm acquisition

Last week EDACafe briefly informed readers about SoftBank reportedly “exploring alternatives including a full or partial sale or public offering” of Arm. A recent update on this story is the news of Nvidia being reportedly interested in acquiring Arm from SoftBank, “in what could become the biggest-ever semiconductor deal.” Anonymous sources quoted by Bloomberg pointed out that “Nvidia’s interest may not lead to a deal, and SoftBank could opt to pursue a listing of the business instead.” Sources also added that “SoftBank approached Apple to gauge its interest in acquiring Arm,” but “Apple isn’t planning to pursue a bid.”

First Intel 7nm product expected for late 2022

Addressing investors during the second quarter earnings webcast, Intel’s CEO Bob Swan also raised the well-known issue of the company’s delay – relative to major foundries – in reaching the 7 nanometer process node. “We are seeing an approximate six-month shift in our 7nm-based CPU product timing relative to prior expectations”, he stated in his prepared remarks. “The primary driver is the yield of our 7nm process, which based on recent data, is now trending approximately twelve months behind our internal target. We have identified a defect mode in our 7nm process that resulted in yield degradation. We’ve root-caused the issue and believe there are no fundamental roadblocks, but we have also invested in contingency plans to hedge against further schedule uncertainty. We’re mitigating the impact of the process delay on our product schedules by leveraging improvements in design methodology such as die disaggregation and advanced packaging. We have learned from the challenges in our 10nm transition and have a milestone-driven approach to ensure our product competitiveness is not impacted by our process technology roadmap.” (…) “We now expect to see initial production shipments of our first Intel-based 7nm product, a client CPU in late 2022 or early 2023. We are also focused on maintaining an annual cadence of significant product improvements independent of our process roadmap, including the holiday refresh window of 2022. In addition, we expect to see initial production shipments of our first Intel-based 7nm data center CPU design in the first half of 2023.”

Bob Swan, Intel’s CEO. (Credit: Walden Kirsch/Intel Corporation)

New algorithm enables training of fully analog neural networks

So far, the low-power benefits of analog neural networks (devices that use a resistor crossbar to perform multiply-accumulate operations in the analog domain) have only been restricted to inference, as the backpropagation algorithm used for training does not fit well with analog technologies. Now a research work from Rain Neuromorphics (Redwood City, CA) and the famous AI scientist Yoshua Bengio promises to break this barrier. The researchers have come up with a method for training end-to-end analog neural networks (where ‘end-to-end’ means that no power-hungry DAC or ADC are required) using an algorithm different from backpropagation. The analog device used by researchers is a memristor crossbar array, and the innovative training algorithm – introduced by Bengio and others in 2017- is called Equilibrium Propagation. Trained on the MNIST classification task, the all-analog AI chip performs comparably or better than equivalent-size software-based neural networks. According to the researchers, this work “can guide the development of a new generation of ultra-fast, compact and low-power neural networks supporting on-chip learning.” From the point of view of the study of biological (real) brains, an interesting aspect of the Equilibrium Propagation algorithm is that – even if applicable to analog networks – it still retains some similarities with backpropagation, which is usually  considered totally implausible for biological brains. For this reason, according to Bengio and the other researchers, Equilibrium Propagation makes it “more plausible that a mechanism similar to Backpropagation could be implemented by brains.”

Yoshua Bengio. Image credit: https://yoshuabengio.org

Standard updates: DDR5, 5G, MPEG-H 3D Audio

JEDEC has published the much-anticipated DDR5 SDRAM standard (which is going to pose new signal integrity challenges in PCB design, as discussed in our special report last April). Speaking of standards, 3GPP has recently announced release 16 of the 5G specifications, focusing on several aspects and applications that go beyond just wide bandwidth for smartphone users. New features concern V2x automotive applications (platooning, automated driving, remote driving), industrial IoT, Ultra-Reliable and Low Latency Communication (URLLC), 5G efficiency (interference mitigation, eMIMO, power consumption etc.), integrated access and backhaul, satellite access, mobile communication system for railways, and more. And German research institute Fraunhofer IIS has announced a licensing program for the new MPEG-H 3D Audio Baseline Profile. A subset of the existing MPEG-H 3D Audio Low Complexity Profile, it enables maximum interoperability with existing devices that have implemented that particular profile while at the same time significantly reducing (up to fifty percent) the implementation and testing effort.

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