Catching up with an announcement that dates back to a few days ago, this week’s news summary places FPGAs in the spotlight. Other news includes the launch of a Palo Alto-based robotics startup, adding to a Bay Area scenario that features at least another innovative robotics company, Covariant (Berkeley, CA). Advancements in discrete and passive components complete this week’s roundup.
Lattice innovates general-purpose FPGAs
Up to twice the I/O density per square millimeter in comparison to similar competing FPGAs: this is what Lattice is claiming for its new family of low-power, general purpose FPGAs, called Certus-NX. Manufactured using a 28 nm FD-SOI process technology, the new devices boast a much smaller package, greater I/O density, and lower power compared to competing FPGAs of similar gate counts. Compactness enables, for example, to create a complete PCIe solution in 36 mm2. Other features of the new FPGAs include instant-on performance (with individual I/Os able to configure in 3 ms, and full-device startup in 8-14 ms depending on device capacity), support for ECDSA authentication, better soft-error rate (SER) performance. Notable IP blocks available on Certus-NX include 1.5 Gbps differential I/O, 5 Gbps PCIe, 1.5 Gbps SGMII, and 1066 Mbps DDR3. A five-page white paper from analyst Linley Gwennap provides a detailed description of the Certus-NX and a comparison with similar FPGAs from Intel and Xilinx.
Image credit: Lattice
