Open-source processor IP keeps improving: SiFive has recently launched the new 20G1 release of its RISC-V Core IP portfolio, claiming up to 2.8x more performance, up to 25% lower power and up to 11% smaller area (“based on SiFive internal engineering measurement”). This is one of the many updates from the last few days, which also include EDA innovations, new Arm rumors, details on Intel’s technology roadmap, AI research advancements, and some standard news.

Mentor boosts analog verification speed

Designers of PLLs and SerDes to be implemented in advanced node geometries will be among the Mentor users who will benefit from the new Analog FastSPICE eXTreme technology, targeted at nanometer-scale verification of large, post-layout analog designs. Citing several innovations – such as new RC circuit reduction algorithms, performance improvements to the Analog FastSPICE core SPICE matrix solver, better device noise analysis capabilities – Mentor claims for the new eXTreme technology a simulation performance boost of 10X compared to its previous-generation Analog FastSPICE offering, and a 3X simulation performance acceleration compared to commercially available solutions at similar accuracy settings. According to Mentor, Analog FastSPICE eXTreme is especially valuable for analog designs containing high levels of parasitic complexity and contact resistance.

Nvidia reportedly interested in Arm acquisition

Last week EDACafe briefly informed readers about SoftBank reportedly “exploring alternatives including a full or partial sale or public offering” of Arm. A recent update on this story is the news of Nvidia being reportedly interested in acquiring Arm from SoftBank, “in what could become the biggest-ever semiconductor deal.” Anonymous sources quoted by Bloomberg pointed out that “Nvidia’s interest may not lead to a deal, and SoftBank could opt to pursue a listing of the business instead.” Sources also added that “SoftBank approached Apple to gauge its interest in acquiring Arm,” but “Apple isn’t planning to pursue a bid.”

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Acquisitions – either officially announced or just rumored about – make up most of our news summary this week. We will then move to some AI chip updates; but first, let’s take a look at one of the EDA announcements that are going to be in the spotlight at this year’s Virtual DAC, running from July 20 to 24.

Early short circuits fixing with Mentor’s Calibre nmLVS-Recon

Mentor has announced the Calibre nmLVS-Recon technology, aimed at speeding overall circuit verification turnaround time by helping designers identify and resolve selected systemic errors early in the development phase. As explained in the announcement’s press release, early design versions typically contain many gross systemic violations. For example, a “shorted nets” class of violation generates millions of errors and is very compute intensive. Circuit verification engineers can use the Calibre nmLVS-Recon short isolation configuration to find and fix these types of violations quickly and efficiently.

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Catching up with an announcement that dates back to a few days ago, this week’s news summary places FPGAs in the spotlight. Other news includes the launch of a Palo Alto-based robotics startup, adding to a Bay Area scenario that features at least another innovative robotics company, Covariant (Berkeley, CA). Advancements in discrete and passive components complete this week’s roundup.

Lattice innovates general-purpose FPGAs

Up to twice the I/O density per square millimeter in comparison to similar competing FPGAs: this is what Lattice is claiming for its new family of low-power, general purpose FPGAs, called Certus-NX. Manufactured using a 28 nm FD-SOI process technology, the new devices boast a much smaller package, greater I/O density, and lower power compared to competing FPGAs of similar gate counts. Compactness enables, for example, to create a complete PCIe solution in 36 mm². Other features of the new FPGAs include instant-on performance (with individual I/Os able to configure in 3 ms, and full-device startup in 8-14 ms depending on device capacity), support for ECDSA authentication, better soft-error rate (SER) performance. Notable IP blocks available on Certus-NX include 1.5 Gbps differential I/O, 5 Gbps PCIe, 1.5 Gbps SGMII, and 1066 Mbps DDR3. A five-page white paper from analyst Linley Gwennap provides a detailed description of the Certus-NX and a comparison with similar FPGAs from Intel and Xilinx.

Image credit: Lattice

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