Foundry roadmaps made news headlines over the past few days, with TMSC reportedly working on an intermediate 4 nanometers node before moving to 3 nanometers. Besides other semiconductor-related updates, interesting news this week also concern the IT industry in general.
EDA/IP updates: Synopsys, Real Intent, Moortec
Synopsys’ DesignWare True Random Number Generator IP has received validation by the NIST Cryptographic Algorithm Validation Program, making it easier for customer end products to obtain Federal Information Processing Standards (FIPS) 140-3 certification.
Verix DFT, a full-chip, multimode DFT static sign-off tool recently unveiled by Real Intent, promises to reduce static sign-off time by several weeks. The new tool is deployed throughout the design process: during RTL design, as part of addressing asynchronous set/reset, clock and connectivity issues early; after scan synthesis, to check for scan chain rule compliance; and following place & route to assess and correct issues with scan-chain reordering or netlist modification. Time savings are gained from lower setup time, runtime speedup, and the reduced engineering debug and violation fixing due to consolidated reporting.
