Microsoft has just announced it will permanently close all its retail stores around the world – except for four “Microsoft Experience Centers” in London, NYC, Sydney, and Redmond campus locations. The company’s retail team members will continue to serve customers from Microsoft corporate facilities and remotely. This was the biggest news today, but many other interesting things happened recently; some of them are summarized below.

Samsung launches its Cloud Design Platform

Last week EDACafe briefly reported about TSMC’s initiative aimed at using Microsoft Azure to speed up timing signoff for advanced-node SoC designs, with two separate collaboration agreements involving Cadence and Synopsys respectively. More cloud-based EDA news this week are coming from Samsung, that has launched its ‘Samsung Advanced Foundry Ecosystem (SAFE) Cloud Design Platform (CDP)’ for fabless customers, in collaboration with Rescale (San Francisco, CA). The two announcements are different in many respects: according to a press release, Samsung Foundry initiative is not focusing on timing signoff only but is offering a virtual “design environment” where customers can use tools from multiple vendors such as Ansys, Cadence, Mentor and Synopsys. Also, instead of collaborating with a single cloud service provider, Samsung Foundry has chosen Rescale’s multi-cloud platform. Rescale partners with several providers such as Amazon Web Service, Microsoft Azure, Google Cloud Platform, IBM, and Oracle Cloud Infrastructure. Common to both initiatives, obviously, is the goal of using cloud resources to speed up processing. Gaonchips – one of Samsung Foundry’s Design Solution Partners – has already tested the SAFE CDP on its 14nm automotive project using Cadence’s Innovus Implementation System and claims a 30 percent reduction of its design run-time compared to current on-premise execution times.

Mentor adds UltraSoC monitoring IP to its Tessent suite

Siemens, Mentor’s parent company, has signed an agreement to acquire UltraSoC (Cambridge,UK), a company providing a modular IP platform that allows to create on-chip monitoring and analytics infrastructures. UltraSoC’s IP is designed to accelerate silicon bring-up, optimize product performance, and confirm that devices are operating “as designed” for functional safety and cybersecurity purposes. Siemens plans to integrate UltraSoC’s technology into the Xcelerator portfolio as part of Mentor’s Tessent software product suite. Together with Tessent’s design-for-test (DFT) solutions, the combined offering is aimed at creating a ‘Design for Lifecycle Management’ solution for system-on-chips.

CMOS device fabrication at 500°C enables 3D monolithic integration

French research institute CEA-Leti is in the news again this week with another paper presented virtually during the 2020 Symposia on VLSI Technology & Circuits. The work, done in collaboration with Samsung, demonstrates the possibility of fabricating FDSOI CMOS devices without exceeding the 500°C temperature threshold. Conventional CMOS manufacturing processes require temperatures higher that 500°C, making it difficult to build 3D monolithic structures, since fabricating the upper-level transistors could damage the metal interconnects and the silicide of the bottom-level transistors. The low-temperature process developed by CEA-Leti for top-level devices prevents deterioration of bottom-level transistors, paving the way to 3D monolithic integration which promises many benefits over die stacking.

Arm-based Japanese supercomputer is number one in TOP500 list

Called Fugaku, the most powerful supercomputer in the world is installed at Riken Center for Computational Science in Kobe, Japan. The machine, powered by Fujitsu’s A64FX processors containing forty-eight Arm cores, is number one in the latest TOP500 supercomputer list – the new edition of the ranking compiled twice a year by experts from Lawrence Berkeley National Laboratory, University of Tennessee Knoxville, and ISC Group (Frankfurt, Germany). With a High Performance Linpack (HPL) result of 415.5 petaflops, Fugaku dramatically outperforms number two on the list, an IBM-built supercomputer called Summit that delivers 148.8 petaflops on HPL. According to Riken Center, Fugaku also swept the competitors taking first place on three different rankings: the HPCG (High-Performance Conjugate Gradient) benchmark, based on real-world applications; HPL-AI, based on tasks typically used in artificial intelligence applications; and Graph 500, based on data-intensive loads. As underlined by Riken Center, this is the first time in history that the same supercomputer has become number one on these three rankings simultaneously. As usual, the TOP500 list provides many interesting insights. Only 144 systems – out of 500 – are using accelerators or coprocessors, the majority of which (135) are equipped with Nvidia GPUs. The x86 continues to be the dominant processor architecture, used by 481 of the 500 systems. Intel claims 469 of these, with AMD installed in 11 and Hygon in the remaining one.  Arm processors are used by just four TOP500 systems, three of which employ the Fujitsu A64FX processor, with the remaining one powered by Marvell’s ThunderX2 processor. Chinese manufacturers lead the list in terms of number of installations with Lenovo (180), Sugon (68) and Inspur (64). The breakdown of system interconnect shows that Ethernet is used in 263 systems, InfiniBand in 150, and the remainder employ custom or proprietary networks.

The Fugaku supercomputer. Image credit: Riken Center for Computational Science

Radar-based blood pressure measurement

Infineon’s Silicon Valley Innovation Center (SVIC), based in Milpitas, has entered in a new agreement with startup Blumio (San Mateo, CA) to co-develop a wearable, non-invasive blood pressure sensor based on Infineon’s XENSIV radar chipset by 2021. Key concept is using a radar sensor to detect the microscopic motions on the surface of the skin caused by pulsation traveling along the artery, then applying proprietary algorithms to extract blood pressure and other heart related metrics from the acquired waveform. According to the German chipmaker, the new sensor has the potential to disrupt the USD 45 billion market for wearable cardiovascular monitoring devices by enabling continuous and precise measurement without a cuff. In its incubator role, the SVIC will provide funding and resources to support the sensor’s commercialization.

Acquisitions

Besides the above-mentioned Siemens-UltraSoC deal, two more acquisition announcements are in the news this week. Preannounced last March, the pending acquisition of Adesto (Santa Clara, CA) by UK-based Dialog Semiconductor is expected to close on June 29, 2020, now that the parties have received the green light from the Committee on Foreign Investment in the United States. And Keysight has completed the acquisition of Eggplant – a software test automation platform provider – from The Carlyle Group.

Advanced semiconductor technology is in the spotlight this week, with some significant innovations that have been presented at the 2020 Symposia on VLSI Technology and Circuits – a virtual event this year. More news concern power devices and embedded software; but first, a few EDA and FPGA updates.

Cloud-based timing signoff: TSMC, Microsoft, Cadence, Synopsys

Leveraging Microsoft Azure cloud computing to speed-up timing signoff for advanced-node SoC designs meant to be fabricated by TSMC: this is the goal of two separate three-way collaboration agreements, one involving Cadence and the other Synopsys. In the case of Cadence, the collaboration concerns the Tempus Timing Signoff Solution and the Quantus Extraction Solution, which customers will use with the Cadence CloudBurst Platform; for Synopsys, tools involved in the agreement are PrimeTime static timing analysis and StarRC parasitic extraction. Both Cadence and Synopsys cited massive parallelization and scalability – made possible by cloud computing – as the major benefits enabling a speed-up in timing signoff. White papers providing more details about these cloud-based solutions are available for TSMC customers in the foundry’s website.

Open source suite of development tools for QuickLogic FPGAs

With its QORC initiative (QuickLogic Open Reconfigurable Computing), QuickLogic claims to be the first programmable logic vendor to actively embrace a fully open source suite of development tools for its FPGA devices and eFPGA technology. The initial offering, developed by Antmicro (Sweden/Poland) in collaboration with QuickLogic and Google, supports QuickLogic’s EOS S3 low power voice and sensor processing MCU with embedded FPGA, and PolarPro 3E discrete FPGA family. The EOS S3 open source development tools suite includes FPGA development flow (SymbiFlow); SoC emulation (Renode); Zephyr real time operating system, running on the Arm Cortex-M4F; and QuickFeather development kit.

Image credit: QuickLogic

Seven-layer gate-all-around FET outperforms FinFETs

French research institute CEA-Leti has demonstrated fabrication of a new gate-all-around (GAA) nanosheet device as an alternative to FinFET technology targeting high-performance applications. Researchers have fabricated GAA nanosheet transistors with seven levels of stacked silicon channels, more than twice as many as state-of-the-art today. By increasing the number of stacked channels, CEA-Leti increased the effective width of the device for a given layout footprint, thus inducing higher drive current and achieving a better DC performance than leading-edge devices. CEA-Leti’s demonstration was based on a “replacement metal-gate” process developed for FinFETs.

First demonstration of GAA NanoSheet transistors with 7 stacked channels from tall and straight (SiGe/Si) fins (15nm≤W≤85nm). Copyright CEA-Leti

Tungsten buried power rails improve SRAM performance at 3 nanometers

Belgian research institute Imec has demonstrated a tungsten buried power rail (BPR) integration scheme in a FinFET CMOS test vehicle, which does not adversely impact the CMOS device characteristics, showing excellent resistance values and electromigration behavior. A complementary study shows the advantages at system level of implementing BPRs as a scaling booster in 3 nanometer SRAM designs. As explained in a press release, buried power rails have recently emerged as an attractive structural scaling booster allowing a further reduction of standard cell height. Power rails are traditionally implemented in the chip’s back-end-of-line (BEOL); BPRs on the contrary are buried in the chip’s front-end-of-line (FEOL) to help free up routing resources for the interconnects. Integrating BPRs within the front-end module is however challenging, as BPR processing may induce stress in the conduction channel or cause metal contamination issues. Imec researchers avoided these problems by burying the W-BPR below the fin, deep into the shallow trench isolation (STI) module, and by capping the BPR metal by dielectric until the end of the processing. In a SRAM, moving the VDD and VSS power lines below the device allows more space for word- and bitline, offering a significant performance boost at system level. Imec simulations showed a 28.2% performance improvement for a server-processor having BPR-SRAMs with respect to conventional SRAM bit cells in L2 and L3 cache.

Imec integrated tungsten Buried Power Rails. Copyright Imec

Voltage-controlled MRAMs gain higher write speed and better manufacturability

Imec has also solved two fundamental operation challenges which have so far limited the write speed and manufacturability of voltage-controlled magnetic anisotropy (VCMA) magnetic random access memories (MRAMs): the need for pre-reading the device before writing, and the need for an external magnetic field during switching. Briefly summarizing the explanation provided in this press release, the pre-read step has been avoided thanks to differentiated voltage thresholds for the two memory states; and the external magnetic field is no longer necessary thanks to a magnetic hardmask embedded on top of the magnetic tunnel junction. With these innovations, VCMA MRAMs fabricated using a 300mm state-of-the-art CMOS infrastructure can achieve nanosecond-scale speed and 20 femtojoule write energy, outperforming STT-MRAMs. According to Imec, VCMA MRAMs are now ideal candidates for high-performance, low-power and high-density memory applications.

Rohm lowers ON resistance for SiC MOSFETs

Rohm Semiconductor has announced the fourth generation of its 1200V SiC MOSFETs, claiming 40% lower ON resistance – while still maintaining short circuit withstand time – and 50% lower switching loss. The company has achieved these advancements over its previous generation SiC MOSFETs by improving their double trench structure and reducing their gate-drain capacitance. Bare chip samples of the new devices have been made available from June 2020, with discrete packages to be offered in the future.

Reduction of ON resistance in Rohm’s SiC MOSFETs. Copyright Rohm

“Mission critical edge” software bundles from Lynx

“Mission critical edge” is the expression coined by Lynx Software Technologies (San Jose, CA) to designate edge computing solutions that require robust system-safety mechanisms, state-of-the-art security, and real time determinism with sub-microsecond latency – such as the ones needed by industrial automation, drones, satellites, and avionics. Now Lynx is addressing this emerging market – which, according to the company, will have a $16 billion SAM in 2023 – with three new bundles based on MOSA.ic, its framework for development and integration of complex multicore safety or security systems. The three new bundles are targeted to industrial, UAVs/satellites, and avionics applications respectively. Built on the LynxSecure separation kernel hypervisor, MOSA.ic supports a variety of operating systems and runs on Intel, Arm and PowerPC processors.

Foundry roadmaps made news headlines over the past few days, with TMSC reportedly working on an intermediate 4 nanometers node before moving to 3 nanometers. Besides other semiconductor-related updates, interesting news this week also concern the IT industry in general.

EDA/IP updates: Synopsys, Real Intent, Moortec

Synopsys’ DesignWare True Random Number Generator IP has received validation by the NIST Cryptographic Algorithm Validation Program, making it easier for customer end products to obtain Federal Information Processing Standards (FIPS) 140-3 certification.

Verix DFT, a full-chip, multimode DFT static sign-off tool recently unveiled by Real Intent, promises to reduce static sign-off time by several weeks. The new tool is deployed throughout the design process: during RTL design, as part of addressing asynchronous set/reset, clock and connectivity issues early; after scan synthesis, to check for scan chain rule compliance; and following place & route to assess and correct issues with scan-chain reordering or netlist modification. Time savings are gained from lower setup time, runtime speedup, and the reduced engineering debug and violation fixing due to consolidated reporting.

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Autonomous vehicles obviously continue to be a hot theme, both in terms of business – with Amazon reportedly in advanced talks to buy self-driving car tech company Zoox (Foster City, CA) – and in terms of technology. Recent AV tech updates include a new standard and improved simulation solutions. More news this week come from academic research on new materials, both for IT and for power applications; lastly, one more FPGA vendor offering simplified solutions for non-expert designers.

Autonomous vehicles updates: UL 4600 standard, news from AVSimulation and Foretellix

The amount of technical standards specifically addressing autonomous vehicles is growing: last week we briefly reported about IEEE 2846, a “formal model for safety considerations in automated vehicle decision making”; and last April 1 Underwriters Laboratories announced the publication of UL 4600, a “standard for safety for the evaluation of autonomous products”.

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