End of year earnings calls continue; this week it’s Cadence’s turn, with Lip-Bu Tan sharing some details about 2019 customers. More news from the last few weeks include some announcements concerning memories, with the addition of updates on neural networks applications and startups developing new processors.
Cadence 2019 results
Cadence reported 2019 revenue of $2.336 billion, compared to revenue of $2.138 billion for 2018. On a GAAP basis, the company achieved an operating margin of 21 percent and a net income of $989 million in 2019, compared to operating margin of 19 percent and net income of $346 million for 2018. As for 2020, Cadence expects total revenue in the range of $2.545 billion to $2.585 billion. On a GAAP basis, operating margin is expected to be 21 to 22 percent. During the financial results conference call, Cadence’s CEO Lip-Bu Tan summarized the company’s major achievements for 2019: among them, about 50 new full-flow wins, including one for new advanced node designs with “a leading maker of FPGA chips”; he also mentioned successes in the digital business – with customers such as MediaTek, Samsung, Socionext, Innovium, Mellanox, Uhnder – and a win for the Xcelium parallel simulator at “a leading U.S. computing company”. Cadence IP royalty growth was strong particularly in the audio market, where Tensilica HiFi DSP processors are increasingly being adopted in True Wireless Stereo based earbuds, and in the next generation of smart speakers. In 2019 Cadence entered the System Analysis market introducing the Clarity 3D Solver and the Celsius Thermal Solver, solutions targeted at electromagnetic field simulation and electro-thermal co-simulation respectively; Lip-Bu Tan said that Cadence is “extremely pleased” with the ramp of these innovative products, with well over 90 evaluations underway and more than 20 customers to date, including Micron, STMicro, Kioxia, Realtek, and Ambarella.
Lip-Bu Tan. Image credit: Cadence
Memory updates: Flash, LP DRAM, ReRAM
A quick roundup of some recent memory updates. Kioxia Europe (formerly Toshiba Memory Europe) has successfully developed its fifth generation BiCS Flash three-dimensional flash memory with a 112-layer vertically stacked structure. The new device has a 512 gigabit (64 gigabytes) capacity with 3-bit-per-cell (triple-level cell) technology. Kioxia plans to start shipping samples for specific applications in the first quarter of this year. Micron Technology has delivered what it claims is the world’s first low-power DDR5 DRAM in mass production, to be used in the soon-to-be-released Xiaomi Mi 10 smartphone. The company is shipping LPDDR5 to customers in capacities of 6GB, 8GB and 12GB and at data speeds of 5.5Gbps and 6.4Gbps. Weebit Nano has launched a program to address the needs of discrete memory components based on its ReRAM memory technology. This broadens the work program for Weebit beyond just the “embedded” non-volatile memory market. According to Weebit, discrete memory chips contain larger memory arrays and are more technically challenging than embedded modules, requiring additional development work before reaching productisation. A key element required for discrete memory chips is called a “selector”, which helps to selectively modify specific cells – while the others are not impacted. The work required for the discrete memory chips will be performed by Weebit in co-operation with French research institute Leti.
The new Kioxia BiCS Flash. Image credit: Kioxia
Neural networks-based video compression
Artificial intelligence is gaining traction in image and video compression. Among the machine learning capabilities that Xilinx is offering to professional audio-video market customers, the ‘Region-of-Interest Encoding’ detects faces and features in the video image so that the H.264/H.265 codec integrated in the Zynq UltraScale+ MPSoC can keep video quality high in those areas, and apply a higher compression for backgrounds. But besides distinguishing faces from background, neural networks can be used for compression itself – and Google has announced the new edition of a workshop specifically devoted to this new application. As noted in a Google AI Blog post, in 2015 researchers demonstrated that neural network-based image compression could yield significant improvements to image resolution while retaining good quality and high compression speed. The Third Workshop and Challenge on Learned Image Compression (CLIC) will be held at the CVPR 2020 conference. Researchers will be challenged to use machine learning, neural networks and other computer vision approaches to increase the quality and lower the bandwidth needed for multimedia transmission. This year’s workshop will include a low-rate image compression challenge (squeezing an image dataset to 0.15 bits per pixel) and a P-Frame video compression challenge.
New server processors promising a tenfold efficiency boost
Back in October 2018, the Microprocessor Report analyzed Tachyum’s Prodigy server processor and concluded: “If [Tachyum] can stick to its plan and deliver compelling performance, hyperscale companies will strongly consider [Prodigy] as an alternative to Intel’s Xeon”. Tachyum – a Silicon Valley based semiconductor startup, with R&D development center in Bratislava, Slovakia – has recently taken a new step towards real-world applications: its Prodigy Processor AI/HPC Reference Design will be used in a supercomputer which will be deployed in 2021. True to its name, the new chip promises prodigious performance: as stated in a Tachyum press release, “in normal datacenter workloads, Prodigy handily outperforms the fastest processors while consuming one-tenth the electrical power, and it is one-third the cost. In AI applications, Prodigy outperforms GPUs and TPUs on neural net training and inference workloads, and is orders of magnitude easier to program”. Prodigy, a 64-core processor with a clock speed in excess of 4GHz, is slated for commercial availability in 2021.
Another company aiming to reduce power consumption in datacenters is Triple-1 (Fukuoka, Japan), that has announced the development of an AI processor called Goku which will be fabricated in a 5-nanometer process. As of today, little details are available in the company’s website. Triple-1 is mostly stressing the power efficiency benefits of using a 5-nanometer process and a manually optimized design. According to Triple-1, there are currently no mass-produced AI chips fabricated in a process geometry smaller than 12-nanometer. Goku, too, promises a tenfold improvement in power efficiency, reaching 10 TFLOPS/W. Expected peak performance (half-precision) is 1 PFLOPS (1,000 TFLOPS). Mass production of Goku is scheduled for 2021.
The Goku processor. Image credit: Triple-1
