EUV lithography and advanced process nodes: challenges and expectations

On one side, a plethora of difficult technological hurdles – such as the ones that will be addressed by the upcoming SPIE conference on advanced lithography. On the other side, major companies developing or using EUV systems – such as ASML and TSMC – confidently expecting that all those hurdles will be overcome. The current status of EUV lithography can probably be considered as a good example of the unshakeable trust in technological progress that has always driven the semiconductor industry. And evidence shows that this trust is well placed: 7-nanometer chips manufactured with EUV lithography are now in volume production. January 2020 earnings conferences from both ASML and TSMC offered some interesting insights on what the industry is expecting from EUV lithography, and the program of the above-mentioned SPIE conference speaks volumes about the challenges implied in those expectations.

ASML forecasting a 60% increase of EUV systems sales in 2020

Let’s start with ASML, the Dutch manufacturer of EUV lithography equipment. On occasion of its recent investor call, ASML’s CEO Peter Wennink disclosed some figures about the company’s EUV business. As Wennink pointed out, 2019 was a breakthrough year in EUV lithography since the technology started being used in high volume production for consumer products available on the market. Also, in 2019 EUV equipment performance increased: ASML started shipping its high-productivity NXE:3400C systems, which made up most of the EUV sales in the fourth quarter (six systems out of eight). The total number of EUV systems shipped by ASML in 2019 amounts to twenty-six, corresponding to full-year sales of around 2.8 billion euros. Increasing customer confidence in EUV is now translating into more layers in logic device production and initial expansion to memory device production. For full-year 2020, ASML is planning for EUV sales of around 4.5 billion euros on 35 systems, which translates to a EUV sales growth of approximately 60 percent. And in fact, orders are pouring in: as detailed by Executive Vice President and Chief Financial Officer Roger Dassen, fourth quarter system bookings include 1.1 billion euros for nine EUV systems. To fulfill the expected strong demand increase, the company is working on cycle time reduction to enable a capacity of 45-50 systems in 2020. Acceleration of the EUV roadmap was the major driver of ASML’s R&D spend in 2019, totaling 2.0 billion euros. And development of high-NA (numerical aperture) EUV systems is underway at both ASML and its suppliers. In particular, high-NA optics is being developed at the German company Zeiss SMT (Semiconductor Manufacturing Technology). High-NA capacity and infrastructure was a major driver of ASML’s CapEx in 2019, amounting to 886 million euros.

Peter Wennink. Image credit: ASML

TSMC: 5nm volume production expected for first half 2020

Let’s now move to Taiwan-based TSMC, a foundry where EUV lithography is already extensively used. As the company’s VP & CFO Wendell Huang pointed out during the recent earnings conference and earnings call, 7-nanometer process technology contributed 35% of TSMC’s total wafer revenue in fourth quarter 2019. On a full year basis, 7-nanometer contribution increased from 9% in 2018 to 27% of wafer revenue in 2019. Out of the anticipated 2020 CapEx ($15 billion to $16 billion), about 80% will be allocated for advanced process technologies including 3, 5 and 7-nanometers. TSMC’s Vice Chairman & CEO C. C. Wei provided details about the various TSMC’s advanced processes: N7 is now in its third year of ramp; high-volume, EUV-based N7+ is entering its second year of ramp; N6 (6-nanometer) is on track for ‘risk production’ in first quarter this year and volume production before the end of this year. TSMC expect its 7-nanometer family (which includes N6) to contribute more than 30% of its wafer revenue in 2020. The company’s N5 technology – the 5-nanometer process, which will adopt EUV extensively – is well on track for volume production in first half this year and with good yield, Wei said. TSMC expect a very fast and smooth ramp of N5 in the second half of this year, driven by both mobile and HPC applications; the 5-nanometer process is therefore projected to contribute about 10% of the company’s wafer revenue in 2020. Finally, TSMC is already working with customers on N3’s design (3-nanometer). More details about N3 will be announced at the TSMC North America Technology Symposium on April 29.

The challenges of advanced lithography in an upcoming SPIE conference

Hurdles abound in EUV lithography – just take a look at the excellent Wikipedia entry on this topic – but brilliant minds around the world are working hard to find solutions, and one can reasonably assume that they will succeed. Many of these minds will gather in San Jose, CA, February 23 to 27, for the SPIE conference on Advanced Lithography. Papers will be addressing seven topics, ranging from EUV lithography to novel patterning materials to advanced etch technology. Two of the papers will provide updates about the effort of ASML and Zeiss who are jointly developing a high-NA solution. Many other papers will address the new challenges posed by high-NA systems on aspects such as managing edge placement error (EPE), angular bandwidth limitations of the mask multilayer requiring the use of anamorphic optics, new multilayer material systems, stochastics defect in photoresist materials and exposure processes, the need for new resists etc. The EUV Photoresist Testing Center of the Berkeley Lab will also participate in the conference with a paper about its Microfield Exposure Tool (MET5). EDA vendors will also play a role in tackling the new challenges posed by high-NA EUV lithography, providing – for example – simulation tools that can be used for predicting probabilities of stochastic defect such as line bridge or breaks, local resist loss, resist profile footing, resist scumming etc. Cadence, Mentor and Synopsys will participate in the SPIE conference with several papers. Synopsys will also be hosting a technical forum with speakers from IBM, SK Hynix and more.

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