Risc-V is making news this week, with the upcoming Risc-V Summit (December 10th to 12th in San Jose, CA) bringing several announcements regarding this open source ISA. Among the other recent news, some interesting updates concerning EDA, IP and power electronics.
Andes adds Risc-V Vector instruction extension
At the Risc-V Summit Andes will be unveiling details of its new AndesCore 27-series of CPU cores. The 27-series is the first licensable Risc-V core to deliver to a production licensee the Risc-V Vector instruction extension (RVV). The cores’ memory subsystem has also been re-architected to support the RVV requirements in terms of memory bandwidth and efficiency. The RVV is especially targeted to complex computation of large volume of matrix data required by emerging applications such as AI, AR/VR, computer vision, cryptography, and multimedia processing. According to Andes, the Risc-V Vector instruction extension differs from advanced SIMD architectures as it provides more flexibility, with scalable data sizes, flexible microarchitecture implementations, and a memory subsystem that can be optimized at the system level. One of the new cores, dubbed NX27V, contains a Vector Processing Unit (VPU) that allows an arbitrary vector length from 64-bit to 512-bit, and even 4096-bit by combining eight vector registers. Computation of integer, fixed point, floating point, and other AI-optimized representations can be any bit-width from 4 bits to 32 bits. Among other architectural innovations, the 27-series supports multiple outstanding memory accesses, so both the scalar and vector processors don’t have to wait for the data during cache misses. In addition, cache pre-fetches allow the memory to prepare data in advance of processor’s needs. Andes describes this new series as “ground-breaking”, claiming that its VPU has been “designed from the ground up to be a Cray-like full vectorization computation unit”, as opposed to “some advanced SIMD” offering only “incremental” performance growth over preexisting SIMD architectures. The 27-series processor beta release has been delivered to Andes’ first licensee in early December 2019; production database release is scheduled for Q1 2020. Initially available will be the 32-bit A27, the 64-bit AX27 (both tailored for applications running Linux) and the above-mentioned NX27V.
